PIC16F616-ESLASHML datasheet(9/172 Pages) APEX

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Preliminary

DS41288A-page 7

PIC16F616/16HV616

2.0

MEMORY ORGANIZATION

2.1

Program Memory Organization

The PIC16F616/16HV616 has a 13-bit program

counter capable of addressing an 8k x 14 program

memory space. Only the first 2K x 14 (0000h-07FFh)

for the PIC16F616/16HV616 is physically imple-

mented. Accessing a location above these boundaries

will cause a wraparound within the first 2K x 14 space.

The Reset vector is at 0000h and the interrupt vector is

at 0004h (see Figure 2-1).

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F616/16HV616

2.2

Data Memory Organization

The data memory (see Figure 2-2) is partitioned into two

banks, which contain the General Purpose Registers

(GPR) and the Special Function Registers (SFR). The

Special Function Registers are located in the first 32

locations of each bank. Register locations 20h-7Fh in

Bank 0 and A0h-BFh in Bank 1 are General Purpose

Registers, implemented as static RAM. Register

locations F0h-FFh in Bank 1 point to addresses 70h-7Fh

in Bank 0. All other RAM is unimplemented and returns

‘0’ when read. The RP0 bit of the STATUS register is the

bank select bit.

RP0

→ Bank 0 is selected

→ Bank 1 is selected

PC<12:0>

0000h

0004h

0005h

07FFh

0800h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

Wraps to 0000h-07FFh

Note:

The IRP and RP1 bits of the STATUS

maintained as ‘0’s.

PIC16F616-E/ML Datasheet(PDF) 9 Page - Cirrus Logic

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