PIC16F616-ESLASHML datasheet(147/172 Pages) APEX

147 / 172 page

Preliminary

DS41288A-page 145

PIC16F616/16HV616

TABLE 15-4:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C

≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

TMCLMCLR Pulse Width (low)

—

μs

VDD = 5V, -40°C to +85°C

VDD = 5V

TWDT

Watchdog Timer Time-out

Period (No Prescaler)

VDD = 5V, -40°C to +85°C

VDD = 5V

TOST

Oscillation Start-up Timer

Period(1, 2)

—

1024

—

TOSC (NOTE 3)

33*

TPWRT

Power-up Timer Period

140

34*

TIOZ

I/O High-impedance from

MCLR Low or Watchdog Timer

Reset

——

2.0

μs

VBOR

Brown-out Reset Voltage

2.0

—

2.2

(NOTE 4)

36*

VHYST

Brown-out Reset Hysteresis

—

37*

TBOR

Brown-out Reset Minimum

Detection Period

100

—

μsVDD ≤ VBOR

These parameters are characterized but not tested.

† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1:

Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-

ation and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values

with an external clock applied to the OSC1 pin. When an external clock input is used, the ‘max’ cycle time

limit is ‘DC’ (no clock) for all devices.

By design.

Period of the slower clock.

To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1

μF and 0.01 μF values in parallel are recommended.

PIC16F616-E/ML Datasheet(PDF) 147 Page - Cirrus Logic

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