PIC16F616-ISLASHSTSQTP datasheet(45/172 Pages) APEX

45 / 172 page

Preliminary

DS41288A-page 43

PIC16F616/16HV616

6.7

Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

• T1SYNC bit of the T1CON register

• TMR1CS bit of the T1CON register

• T1OSCEN bit of the T1CON register (can be set)

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

6.8

Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

The device will wake-up on an overflow. If the GIE bit of

the INTCON register is set, the device will call the

Interrupt Service Routine (0004h) on an overflow. If the

GIE bit is clear, execution will continue with the next

instruction.

6.9

ECCP Capture/Compare Time Base

The ECCP module uses the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

In Compare mode, an event is triggered when the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

For more information, see Section 10.0 “Enhanced

Capture/Compare/PWM (With Auto-Shutdown and

Dead Band) Module”.

6.10

ECCP Special Event Trigger

When the ECCP is configured to trigger a special

event, the trigger will clear the TMR1H:TMR1L register

pair. This special event does not cause a Timer1 inter-

rupt. The ECCP module may still be configured to gen-

erate a ECCP interrupt.

In this mode of operation, the CCPR1H:CCPR1L

Timer1.

Timer1 should be synchronized to the FOSC to utilize

the Special Event Trigger. Asynchronous operation of

Timer1 can cause a Special Event Trigger to be

missed.

In the event that a write to TMR1H or TMR1L coincides

with a Special Event Trigger from the ECCP, the write

will take precedence.

For more information, see Section 10.2.4 “Special

Event Trigger”.

6.11

Comparator Synchronization

The same clock used to increment Timer1 can also be

used to synchronize the comparator output. This

feature is enabled in the Comparator module.

When using the comparator for Timer1 gate, the

comparator output should be synchronized to Timer1.

This ensures Timer1 does not miss an increment if the

comparator changes.

For

information,

see

Section 8.8.2

“Synchronizing Comparator C2 Output to Timer1”.

FIGURE 6-2:

TIMER1 INCREMENTING EDGE

Note:

The TMR1H:TTMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1:

Arrows indicate counter increments.

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

PIC16F616-I/STSQTP Datasheet(PDF) 45 Page - Cirrus Logic

PIC16F616-I/STSQTP Datasheet(HTML) 45 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL