25CSM04T-ISLASHMF datasheet(15/55 Pages) MICROCHIP

15 / 55 page

 2019-2022 Microchip Technology Inc. and its subsidiares

DS20005817D-page 15

25CSM04

4.4

Hold Function

The HOLD pin is used to pause the serial

communication with the device without having to stop

or reset the clock sequence. The Hold mode, however,

does not have an effect on the internal write cycle.

Therefore, if a write cycle is in progress, asserting the

HOLD pin will not pause the sequence and the write

cycle will continue until it is finished.

The Hold mode can only be entered while the CS pin is

asserted. The Hold mode is activated by asserting the

HOLD pin during the SCK low pulse. If the HOLD pin is

asserted during the SCK high pulse, then the Hold

mode will not be started until the beginning of the next

SCK low pulse. The device will remain in the Hold

mode as long as the HOLD pin and CS pin are

asserted.

While in Hold mode, the SO pin will be in a high-imped-

ance state. In addition, both the SI pin and the SCK pin

will be ignored. The WP pin, however, can still be

asserted or deasserted while in the Hold mode.

To end the Hold mode and resume serial communica-

tion, the HOLD pin must be deasserted during the SCK

low pulse. If the HOLD pin is deasserted during the

SCK high pulse, then the Hold mode will not end until

the beginning of the next SCK low pulse.

If the CS pin is deasserted while the HOLD pin is still

asserted, then any sequence that may have been

started will be aborted.

FIGURE 4-2:

HOLD MODE

4.5

Write Protection

The 25CSM04 write protection schemes are first

controlled by the state of Write Protection Mode (WPM)

bit in the STATUS register (bit 7, byte 1). The device

can be set for either Legacy Write Protection mode or

Enhanced Write Protection mode by the state of the

WPM bit.

The write protection mode can be made permanent by

executing the FRZR instruction. This can be done in

both Legacy Write Protection mode and Enhanced

Write Protection mode. Refer to Section 4.5.4 “Freeze

Memory Protection Configuration (FRZR)” for

details.

4.5.1

LEGACY WRITE PROTECTION

MODE

In Legacy Write Protection mode, the EEPROM array

can only be programmed in accordance with how the

Block Protect bits in the STATUS register are

programmed.

Refer

Section 6.1.2

“Block

Write-Protect Bits” for details.

Additionally, the contents of the STATUS register can

be protected by enabling the Write-Protect Enable

(WPEN) bit in the STATUS register.

When the WPEN function is enabled, the STATUS reg-

ister contents will be protected when the WP pin is

asserted (low). Details about the WPEN function are

provided in Section 6.1.1 “Write-Protect Enable Bit”.

4.5.2

ENHANCED WRITE PROTECTION

MODE

In Enhanced Write Protection mode, the EEPROM

protection is determined by the contents of the Memory

Partition Registers (MPR). Each MPR can be

programmed to specify the ending address of a given

partition as well as to set the desired protection

behavior of that partition.

Full details about the Memory Partition registers can be

found in Section 10.0 “Memory Partition Functional-

ity”.

HOLD

Hold

SCK

Hold

Note:

If Enhanced Write Protection mode is

disabled, the MPRs will be ignored

regardless of their configured behavior.

25CSM04T-I/MF Datasheet(PDF) 15 Page - Microchip Technology

25CSM04T-I/MF Datasheet(HTML) 15 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL