25CSM04T-ISLASHCS0668 datasheet(31/55 Pages) MICROCHIP

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DS20005817D-page 31

25CSM04

FIGURE 9-2:

WRITE SECURITY REGISTER (WREX) BYTE WRITE SEQUENCE

FIGURE 9-3:

WRITE SECURITY REGISTER (WREX) PAGE WRITE SEQUENCE

FIGURE 9-4:

LOCK SECURITY REGISTER (LOCK) SEQUENCE

SCK

2 3 4

567

9 10 11 12

10 0 0 0 0

1 0

WREX Opcode (82h)

Address Bits A23-A0(2)

XX X X X X

D7 D6 D5 D4 D3 D2 D1 D0

Data In

MSb

AA A

Note 1:

This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

A23 through A9 are “don't care” bits, except A10 which must be a logic ‘0’ and A8 which must be a logic ‘1’ to address the

second Security register byte that is user programmable.

High-Impedance

TWC(1)

SCK

234

567

Data In Byte n (256 max.)

MSb

1 0 000 01 0 X X X

AAA

WREX Opcode (82h)

Data In Byte 1

MSb

D7 D6 D5 D4 D3 D2 D1 D0

High-Impedance

833

Address Bits A23-A0(2)

TWC(1)

Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

2: A23 through A9 are “don't care” bits, except A10 which must be a logic ‘0’ and A8 which must be a logic ‘1’ to address

the second Security register byte that is user programmable.

SCK

234

567

9 10 11 12

High-Impedance

1 0 0 0 00

LOCK Opcode (82h)

XX XX X X

XX X X X X 1 X

MSb

XX X

833

Note 1:

This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

A23 through A0 are “don't care” bits, except A10 which must be a logic ‘1’.

Address Bits A23-A0(2)

Data In (xxxxxx1xb)

TWC(1)

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