QPC3624

75Ω 47−2000 MHz Digital Step Attenuator

Data Sheet Rev.5, 7 Dec, 2016 | Subject to change without notice

- 13 of 19 -

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®

Pad Configuration and Description

24

1

2

3

4

5

6

23

22

21

20

19

18

17

16

15

14

13

7

8

9

10

11

12

6-BIT DSA

LOGIC CONTROL

GND

VDD

PBAR/S

GND

RFIN

GND

SI

CLK

LE

GND

RFOUT

GND

Top View

Pad No.

Label

Description

1, 4, 6, 7, 8, 9, 10,

12, 13, 15

GND

Ground Pad

2

VDD

Positive Supply Voltage

3

PBAR/S

Mode Select Pad, Logic Low = Parallel, Logic High = Serial

5

RF Input Pad. Incident RF power must enter this pad for rated thermal performance and reliability

Do not apply DC power to this pad. Pad may be DC grounded externally and is grounded thru resistors internal

to the part.

11

VSS

External Negative Supply Voltage. Grounding pin enables on-chip negative voltage generator. Apply negative

voltage to disable on-chip generator.

14

RF Output Pad; Do not apply DC power to this pad. Pad may be DC grounded externally and is grounded thru

resistors internal to the part.

16

LE

Latch Enable. The leading edge of signal on LE causes the attenuator to change states for serial and latched

parallel modes. For direct parallel mode, keep LE at a logic high level.

17

CLK

Serial Clock Input

18

SI

Serial Data Input

19

C16

16 dB Parallel Control Bit

20

C8

8 dB Parallel Control Bit

21

C4

4 dB Parallel Control Bit

22

C2

2 dB Parallel Control Bit

23

C1

1 dB Parallel Control Bit

24

C0.5

0.5 dB Parallel Control Bit

Backside Paddle

RF/DC GND

RF/DC ground. Use recommended via pattern to minimize inductance and thermal resistance. See PCB

Mounting Pattern for suggested footprint.