IPS2200_V01 datasheet(13/37 Pages) RENESAS

13 / 37 page

IPS2200 Datasheet

Aug.5.22

Page 13

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

VDDOUT_CM

Output DC offset voltage, common

mode voltage

All modes

47.5

52.5

%VDD

DCOFFDRIFT

DC offset voltage drift

Over temperature range

-50

μV/°C

DCOFF

DC offset voltage after trimming

At trim temperature,

over gain range and

transmitter frequency

range, VDD= 3.0 to 5.5V

-6

IOUT3

Output current; 3.3V option

Output load current

-1

IOUT5

Output current; 5V option

-2

IOL

Output overload current,

CRAW_l

Capacitive load, EMC filters

Refer to section 18 for

CO1 to CO4

Noise

Device output noise

Maximum gain,

maximum setting for

integration cycles, no

output filtering, shorted

coil inputs

mVrms

COUT1

Output filter capacitors

For improved EMC

immunity, placed close

to IC output

COUT2

COUT3

COUT4

Table 13. Back-End Specification, Quadrature Pulse Output Option, Pins A, A_N, B, and B_N

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

VQUAD_OH

High level output voltage

Sign of demodulated input voltage:

high = positive; low = negative

100

%VDD

VQUAD_OL

Low level output voltage

IO_QUAD3

Output current; 3.3V option

Output load current

-0.5

+0.5

IO_QUAD5

Output current; 5V option

-1

CRAW_l

Capacitive load

VQUAD_TH_POS

Output switching positive

threshold

Comparator levels for changing

state of A, A_N, B, B_N digital

outputs, relative to amplified input

voltage

VOUT_CM+

0.05

VQUAD_TH_NEG

Output switching negative

threshold

VOUT_CM-

0.05

VQUAD_TH_HYST

Quadrature pulse

hysteresis

Relative to opposite channel

R1(Sin) vs. R2(Cos)

[a]

See Table 2 regarding which of the pins OUT1, OUT2, OUT3, and OUT4 are assigned as A, A_N, B, and B_N.

Table 14. Digital Control Interface, Pins CSN_IRQN, SIO_SDA, SCK_SCL

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

VIH

High level input voltage,

all modes

CSN_IRQN address

select input,

SCK_SCL clock input,

SIO_SDA data input

100

%VDD

VIL3

Low level input voltage,

3.3V mode

%VDD

VIL3

Low level input voltage,

5V mode

%VDD

ILEAK

Input leakage current

-5

µA

VI_HYST

Input hysteresis

SCK_SCL clock input

100

VOH

High level output voltage

All modes

100

%VDD

VOL_PP

Low level output voltage

– push/pull

Push/pull output

CSN_IRQN

%VDD

VOL_OD

Low level output voltage

– open drain

Open-drain output

SIO_SDA, 3mA sink

current

0.4

VIRQN_H

Over-voltage detection at

CSN_IRQN, SCK_SCL,

or SIO_SDA

Over-voltage on these

pins can be monitored

as a diagnostic feature

6.9

7.4

7.9

RSDA,

RSCL,

RSIO,

RSCK

External pull-up resistor

at pins SIO_SDA and

SCK_SCL

Resistor value and

capacitive load on these

pins are limiting the

1.8

4.7

kΩ

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