IPS2200 Datasheet

Aug.5.22

Page 21

11. Block Diagram

Figure 12 shows the block diagram of the IPS2200.

Power

Management

Configuration,

NVM

Oscillator

Rx Sine

Rx

Cosine

Programming

Interface (SPI, I2C)

Tx

RX1

RX2

RX3

RX4

TX1

TX2

CSN_IRQN

(SSN chip select for SPI or

IRQN interrupt for I2C or SPI)

Analog Front-End,

Demodulation,

Gain Adjustment

OUT1

OUT2

OUT3

OUT4

Sin_n / A_n

Diagnostics, Timer

SIO_SDA

SCK_SCL

Gain

Control

gain Sin

Protection

GND

VDDA

VDD

Offset

Control

gain Cos

offset Sin

offset Cos

IPS2200

Figure 12. Block Diagram

The main building blocks include the following:

•

Power Management: power-on-reset (POR) circuit; low drop-out (LDO) regulators for analog and digital

supplies.

•

Oscillator: generation of the transmitter coil signal.

•

Analog Front-End:

o

Input filter, offset, and gain setting: analog AM signal preconditioning.

o

Synchronous integrator: demodulation of the AM signal.

•

Offset Control: correction of offsets at the receiver coil inputs RX1/RX2 and RX3/RX4.

•

Gain Control: correction of amplitude mismatching from RX1/RX2 and RX3/RX4 input signals.

•

Configuration, NVM: nonvolatile storage of factory and user-programmable settings.

•

Programming Interface: configuration, communication, and diagnostics via selectable I2C or SPI bidirectional

interface.

•

Diagnostics, Timer: Diagnostics for critical blocks to ensure functional safety and watchdog timer.

•

Protection: over-voltage, reverse polarity and short circuit protection.

There are four interface options for the OUT1, OUT2, OUT3, and OUT4 pins (see Table 2):

•

Differential analog output

•

Single-ended analog output with reference

•

Incremental digital AB pulse output (one pulse per phase)