LMK6C datasheet(14/45 Pages) TI

14 / 45 page

9 Detailed Description

9.1 Overview

The LMK6x is a fixed-frequency BAW based oscillator that can provide ultra-low jitter both for differential and

single-ended output types.

9.2 Functional Block Diagram

BAW

VDD

CLK_P

Output

Divider

Memory

GND

Power

Conditioning

Temp

Sensor

TCF

Interface &

control logic

Signal Path

Logic

CLK_N

9.3 Feature Description

9.3.1 Bulk Acoustic Wave (BAW)

TI’s BAW resonator technology uses piezoelectric transduction to generate high-Q resonance at 2.5 GHz. The

resonator is defined by the quadrilateral area overlaid by top and bottom electrodes. Alternating high- and

low-acoustic impedance layers form acoustic mirrors beneath the resonant body to prevent acoustic energy

leakage into the substrate. Furthermore, these acoustic mirrors are also placed on top of the resonator stack

to protect the device from contamination and minimize energy leakage into the package materials. This unique

dual-Bragg acoustic resonator (DBAR) allows efficient excitation without the need of costly vacuum cavities

around the resonator. As a result, TI’s BAW resonator is immune to frequency drift caused by adsorption of

surface contaminants and can be directly placed in a non-hermetic plastic package with the oscillator IC in small

standard oscillator footprints.

9.3.2 Device Block-Level Description

High-Q resonant tank of BAW die is complimented with an ultra-low noise oscillator on a base die, designed in

CMOS process node. Temperature variations of oscillation frequency are continuously monitored by a co-located

precision temperature sensor. Correction for frequency is done using an advance signal processing algorithm

which runs continuously in the background while making use of per part calibration coefficients, stored in

NVM, to compensate frequency within ±10 ppm. A very low jitter, low power fractional output divider (FOD) in

the frequency correction path allows necessary compensation with minimum impact to the phase jitter while

generating a per-programmed output frequency clock. The output driver is capable of providing both single-

ended LVCMOS and differential LVPECL, LVDS, and HCSL output formats. Finally, a small power-reset-clock

management system consisting of several low noise LDOs and digital controller makes sure noise sensitive

modules work with enough isolation while maintaining output clock fidelity.

9.3.3 Function Pin(s)

The function pin is identified as pin 1 on the LMK6C and pin 1 or pin 2, depending on the grade of the device,

for the LMK6P, LMK6D, and LMK6H. In addition to output enable, the function pin is also capable of providing

a chip disable / standby feature. In this mode, all blocks will be powered down to provide a maximum current

consumption savings for a non-operation mode, meaning the output clock is not available. The return to the

output clock active time corresponds to the initial start-up time.

The function pin can also be designed to be active high or active low. This allows for compatibility and drop

in replacement with hardware that may have terminated to ground. Contact your TI representative to discuss

options not listed on Figure 5-1 and Figure 5-2.

LMK6C

SNAS826A – APRIL 2022 – REVISED JULY 2022

www.ti.com

Submit Document Feedback

Product Folder Links: LMK6C

LMK6C Datasheet(PDF) 14 Page - Texas Instruments

LMK6C Datasheet(HTML) 14 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL