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F2950 Datasheet(PDF) 3 Page - Renesas Technology Corp |
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F2950 Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 19 page ![]() F2950 Datasheet R35DS0038EU0101 Rev.1.01 Mar 9, 2022 Page 3 1. Pin Information 1.1 Pin Assignments RF2 VCTL GND RF1 VCC F2950 1 2 3 6 5 4 EP RFC Figure 2. Pin Assignments – Top View 1.2 Pin Descriptions Pin Name Function 1 VCTL Logic control pin. See Table 3 for logic control states. 2 RFC RF common port. Matched to 50Ω in the insertion loss state only. If this pin is not 0V DC, then an external coupling capacitor must be used. 3 VCC Power supply. Bypass to GND with capacitors as close as possible to the pin. 4 RF2 RF2 port. Matched to 50Ω in the insertion loss state only. If this pin is not 0V DC, then an external coupling capacitor must be used. 5 GND Ground. Ground this pin as close to the device as possible. 6 RF1 RF1 port. Matched to 50Ω in the insertion loss state only. If this pin is not 0V DC, then an external coupling capacitor must be used. - EP Exposed pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground vias are also required to achieve the specified RF performance. |
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