STM32H725AE datasheet(33/283 Pages) STMICROELECTRONICS

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DS13311 Rev 3

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STM32H725xE/G

Functional overview

3.12

DMA controllers

The devices feature four DMA instances and a DMA request router to unload CPU activity:

•

A master direct memory access (MDMA)

The MDMA is a high-speed DMA controller, which is in charge of all types of memory

transfers (peripheral to memory, memory to memory, memory to peripheral), without

any CPU action. It features a master AXI interface and a dedicated AHB interface to

access Cortex®-M7 TCM memories.

The MDMA is located in D1 domain. It is able to interface with the other DMA

controllers located in D2 domain to extend the standard DMA capabilities, or can

manage peripheral DMA requests directly.

Each of the 16 channels can perform single block transfers, repeated block transfers

and linked list transfers.

•

Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request

router capabilities.

•

One basic DMA (BDMA) located in D3 domain, with request router capabilities.

•

A DMA request multiplexer (DMAMUX)

The DMA request router could be considered as an extension of the DMA controller. It

routes the DMA peripheral requests to the DMA controller itself. This allowing

managing the DMA requests with a high flexibility, maximizing the number of DMA

requests that run concurrently, as well as generating DMA requests from peripheral

output trigger or DMA event.

3.13

Chrom-ART Accelerator (DMA2D)

The Chrom-Art Accelerator (DMA2D) is a specialized DMA dedicated to image manipulation.

It can perform the following operations:

•

Filling a part or the whole of a destination image with a specific color

•

Copying a part or the whole of a source image into a part or the whole of a destination

•

image

•

Copying a part or the whole of a source image into a part or the whole of a destination

•

image with a pixel format conversion

•

Blending a part and/or two complete source images with different pixel format and copy

•

the result into a part or the whole of a destination image with a different color format.

•

All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel

with indexed or direct color mode, including block based YCbCr to handle JPEG

decoder output.

•

The DMA2D has its own dedicated memories for CLUTs (color look-up tables).

An interrupt can be generated when an operation is complete or at a programmed

watermark.

All the operations are fully automated and are running independently from the CPU or the

DMAs.

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