STM32H725AE datasheet(35/283 Pages) STMICROELECTRONICS

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DS13311 Rev 3

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STM32H725xE/G

Functional overview

3.17

Flexible memory controller (FMC)

The FMC controller main features are the following:

•

Interface with static-memory mapped devices including:

–

Static random access memory (SRAM)

–

NOR Flash memory/OneNAND Flash memory

–

PSRAM (4 memory banks)

–

NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

•

Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

•

8-,16-, 24-bit data bus width

•

Independent Chip Select control for each memory bank

•

Independent configuration for each memory bank

•

Write FIFO

•

Read FIFO for SDRAM controller

•

The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the

FMC kernel clock divided by 2.

3.18

Octo-SPI memory interface (OCTOSPI)

The OCTOSPI is a specialized communication interface targeting single, dual, quad or octal

SPI memories. The STM32H725xE/G embeds two separate Octo-SPI interfaces.

Each OCTOSPI instance supports single/dual/quad/octal SPI formats. multiplexing of

single/dual/quad/octal SPI over the same bus can be achieved using the integrated Octo-

SPI I/O manager (OCTOSPIM).

The OCTOSPI can operate in any of the three following modes:

•

Indirect mode: all the operations are performed using the OCTOSPI registers

•

Status-polling mode: the external memory status register is periodically read and an

interrupt can be generated in case of flag setting

•

Memory-mapped mode: the external memory is memory mapped and it is seen by the

system as if it was an internal memory supporting both read and write operations.

The OCTOSPI supports two frame formats supported by most external serial memories

such as serial PSRAMs, serial NAND and serial NOR Flash memories, Hyper RAMs and

Hyper Flash memories.

Multi chip package (MCP) combining any of the above mentioned memory types can also

be supported.

•

The classical frame format with the command, address, alternate byte, dummy cycles

and data phase

•

The HyperBus™ frame format.

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