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HT47C10L Datasheet(PDF) 13 Page - Holtek Semiconductor Inc |
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HT47C10L Datasheet(HTML) 13 Page - Holtek Semiconductor Inc |
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13 / 38 page ![]() HT47C10L Rev. 1.90 13 November 30, 2005 Timer/Event Counter One 16-bit timer/event counter or RC type A/D converter is implemented in the HT47C10L. The ADC/TM bit (bit 1 of ADCR register) decides whether timer A and timer B are composed of one 16-bit timer/event counter or timer A and timer B are composed of RC type A/D converter. The TMRAL, TMRAH, TMRBL, TMRBH composed of one 16-bit timer/event counter, when ADC/TM bit is ²0². The TMRBL and TMRBH are timer/event counter preload registers for lower-order byte and higher-order byte respectively. The timer/event counter clock source comes from system clock (fSYS) or external source (A/D clock from pad:RCIN). The external clock input allows the user to count external events, count external RC type A/D clock, measure time in- tervals or pulse widths, or generate an accurate time base. There are six registers related to the timer/event counter operating mode. TMRAH ([20H]), TMRAL ([21H]), TMRC ([22H]), TMRBH ([23H]), TMRBL ([24H]) and ADCR ([25H]). Writing to TMRBL only writes the data into a low byte buffer, and writing to TMRBH will write the data and the contents of the low byte buffer into the time/event coun- ter preload register (16-bit) simultaneously. The timer/event counter preload register is changed by writ- ing to TMRBH operations and writing to TMRBL will keep the timer/event counter preload register unchanged. Reading TMRAH will also latch the TMRAL into the low byte buffer to avoid the false timing problem. Reading TMRAL returns the contents of the low byte buffer. In other words, the low byte of the timer/event counter can not be read directly. It must read the TMRAH first to make the low byte contents of timer/event counter be latched into the buffer. The TMRC is the timer/event counter control register, which defines the timer/event counter options. The timer/event counter control register define the operating mode, counting enable or disable and active edge. Writ- ing to timer B location puts the starting value in the timer/event counter preload register, while reading timer A yields the contents of the timer/event counter. Timer B is timer/event counter preload register. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source (A/D clock) comes from an external (RCIN) pin. The timer mode functions as a normal timer with the clock source coming from the internal clock source (fSYS). Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (A/D clock from pad:RCIN). The counting is based on the system clock (fSYS). In the event count, A/D clock or internal timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter (TMRAH and TMRAL) to FFFFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register (TMRBH and TMRBL) and generates the corresponding interrupt request flag (TF; bit 4 of INTC) at the same time. In the pulse width measurement mode with the TON and TE bits equal to one, once the RCIN has received a transient from low to high (or high to low if the TE bit is 0) it will start counting until the A/D Clock returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the acti- vated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, T E S y s t e m C l o c k ( f S Y S ) T M 1 T M 0 T O N P u l s e W i d t h M e a s u r e m e n t M o d e C o n t r o l T i m e r / e v e n t c o u n t e r ( 1 6 b i t T i m e r A ) T i m e r / e v e n t c o u n t e r P r e l o a d R e g i s t e r ( 1 6 b i t T i m e r B ) D a t a B u s R e l o a d O v e r f l o w T M 1 T M 0 R C I N A D C / T M = 0 A D E N M O D E T O N T M 0 A D C / T M A D E N R t o F c o n v e r t e r ( A D C R B i t - 2 ) M o d e R R E F R S E N C o n t r o l 2 2 0 0 p F 3 0 k W 2 0 k W ~ 6 0 k W A / D C l o c k Timer/Event Counter |
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