Pad No.

X

Y

Pad No.

X

Y

Pad No.

X

Y

18

-1921.00

-64.65

57

1914.90

-1751.90

96

654.90

1760.40

19

-1921.00

-164.65

58

1918.10

-1465.70

97

554.90

1760.40

20

-1921.00

-264.65

59

1918.10

-1365.70

98

454.90

1760.40

21

-1921.00

-364.65

60

1918.10

-1265.70

99

354.90

1760.40

22

-1921.00

-464.65

61

1918.10

-1165.70

100

254.90

1760.40

23

-1921.00

-564.65

62

1918.10

-1065.70

101

154.90

1760.40

24

-1921.00

-664.65

63

1918.10

-965.70

102

54.90

1760.40

25

-1921.00

-764.65

64

1918.10

-865.70

103

-45.10

1760.40

26

-1921.00

-864.65

65

1918.10

-765.70

104

-145.10

1760.40

27

-1921.00

-964.65

66

1918.10

-665.70

105

-245.10

1760.40

28

-1921.00

-1064.65

67

1918.10

-565.70

106

-345.10

1760.40

29

-1921.00

-1164.65

68

1918.10

-465.70

107

-445.10

1760.40

30

-1921.00

-1264.65

69

1918.10

-365.70

108

-545.10

1760.40

31

-1612.45

-1747.70

70

1918.10

-265.70

109

-645.10

1760.40

32

-1512.45

-1747.70

71

1918.10

-160.40

110

-745.10

1760.40

33

-1412.45

-1747.70

72

1918.10

-60.40

111

-845.10

1760.40

34

-1258.55

-1639.80

73

1918.10

39.60

112

-945.10

1760.40

35

-1115.95

-1639.80

74

1918.10

139.60

113

-1045.10

1760.40

36

-980.55

-1639.80

75

1918.10

239.60

114

-1145.10

1760.40

37

-833.65

-1639.80

76

1918.10

339.60

115

-1245.10

1760.40

38

-698.25

-1639.80

77

1918.10

439.60

116

-1345.10

1760.40

39

-552.95

-1639.80

78

1918.10

539.60

117

-1445.10

1760.40

Pad Description

Pad No.

Pad Name

I/O

Description

1~17

71~117

SEG47~SEG63

SEG0~SEG46

O

LCD segment outputs

18~33

55~70

COM31~COM16

COM0~COM15

O

LCD common outputs, under 80

´16 command mode, COM16~COM31 will

be shared with SEG64~SEG79. COM31/SEG64, COM30/SEG65,

COM29/SEG66....., COM18/SEG77, COM17/SEG78, COM16/SEG79

34

CS

I

Chip selection input with pull-high resistor. When the CS is logic high, the

data and command read from or write to the HT1650 are disabled. The serial

interface circuit is also reset. But if the CS is at a logic low level and is input to

the CS pad, the data and command transmission between the host controller

and the HT1650 are all enabled.

35

RD

I

READ clock input with pull-high resistor. Data in the RAM of the HT1650 are

clocked out on the falling edge of the RD signal. The clocked out data will ap-

pear on the data line. The host controller can use the next rising edge to latch

the clocked out data.

36

WR

I

WRITE clock input with pull-high resistor. Data on the DATA line are latched

into the HT1650 on the rising edge of the WR signal.

37~40

DB0~DB3

I/O

Parallel data input/output with pull-high resistor

41

VSS

¾ Negative power supply for logic circuit, ground

42

43

OSCI

OSCO

I

O

The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to

generate a system clock. If the system clock comes from an external clock

source, the external clock source should be connected to the OSCI pad. But

if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left

open.

44

VDD

¾ Positive power supply for logic circuit

45

VLCD

I

Power supply for LCD driver circuit

46

IRQ

O

Time base or Watchdog Timer overflow flag, NMOS open drain output.

47, 48

BZ, BZ

O

2kHz or 4kHz frequency output pair (tristate output buffer)

49~53

T1~T4, T000

I

Vary bias current pin

It is usually not connected

HT1650

Rev. 1.20

4

November 10, 2005