LEOAC08 datasheet(5/17 Pages) STMICROELECTRONICS

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Symbol

Parameter

Test condition

VCC

(V)

Min.

Typ.

Max.

Unit

VIC-

Negative input clamp

voltage

For input under test, IIN = -1.0 mA

Open

0.4

1.5

IIH

Input current high

For input under test, VIN = VCC

For all other inputs, VIN = VCC or GND

5.5

µA

IIL

Input current low

For input under test, VIN = GND

For all other inputs, VIN = VCC or GND

-1

µA

ICCH

Quiescent supply

current, output high

For all inputs, VIN = VCC or GND IOUT = 0 A

5.5

μA

ICCL

Quiescent supply

current, output low

For all inputs, VIN = VCC or GND IOUT = 0 A

5.5

µA

CIN (3)

Input capacitance

Ta = +25 °C

CPD (4)

(3)

Power dissipation

capacitance

Ta = +25 °C, F = 1 MHz

Tr, Tf

Output rise time and fall

time

CL = 2 pF, RL = 500 ohm (see Figure 2)

3.3

4.5

2.7

CL = 50 pF, RL = 500 ohm (see Figure 2)

4.6

4.5

3.3

TPHL (5)

Propagation delay time

An to Yn, high to low

CL = 50 pF, RL = 500 ohm (see Figure 2)

11.5

4.5

8.5

TPLH(5)

Propagation delay time

An to Yn, low to high

CL = 50 pF, RL = 500 ohm (see Figure 2)

12.5

4.5

1. The VOH and VOL tests shall be tested at VCC = 3.0 V and 4.5 V. The VOH and VOL tests are guaranteed, if not tested, for

other values of VCC. Limits shown apply to operation at VCC = 3.3 V, ±0.3 V and VCC = 5.0 V ±0.5 V. Tests with input current

at +50 mA and –50 mA are performed on only one input at a time with duration not to exceed 10 ms. Transmission driving

tests may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for VIN = VIH

minimum and VIL maximum.

2. The VIH and VIL tests are not required if applied as forcing functions for VOH and VOL tests.

3. CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect

capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. CPD shall be

tested in accordance with the latest revision of JEDEC Standard JESD20 and table IA herein. For CIN and CPD, test all

applicable pins on five devices with zero failures.

4. Power dissipation capacitance (CPD) determines both the power consumption (PD) and dynamic current consumption (IS).

Where: PD = (CPD + CL) (VCC x VCC) f + (ICC x VCC) and IS = (CPD + CL) VCC x f + ICC, and f is the frequency of the input

signal and CL is the external output load capacitance.

5. For propagation delay tests, all paths are tested. The AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and

guaranteed by testing at VCC = 4.5 V. The AC limits at VCC = 3.6 V are equal to the limits at VCC = 3.0 V and guaranteed by

testing at VCC = 3.0 V. Minimum AC limits for VCC = 5.5 V and VCC = 3.6 V are 1.0 ns and guaranteed by guard banding the

VCC = 4.5 V and VCC = 3.0 V minimum limits, respectively, to 1.5 ns. For propagation delay tests, all paths must be tested.

LEOAC08

Electrical characteristics

DS13855 - Rev 2

page 5/17

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