MB91F158 datasheet(13/90 Pages) FUJITSU

13 / 90 page

MB91F158

The following figure shows an example usage of an external clock.

Figure 3.1 An example usage of an external clock

• Care during operating of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even

when there is no external oscillator or external clock input is stopped. Performance of this operation, however,

cannot be guaranteed.

• Watchdog timer function

The watchdog timer supported by the FR family monitors the program that performs the reset delay operation

for a specified time. If the program hangs and the reset delay operation is not performed, the watchdog timer

resets the CPU. Therefore, once the watchdog timer is enabled, operation continues until the CPU is reset.

As an exception, a reset delay automatically occurs if the CPU stops program execution. For the conditions

that apply to this exception, refer to the section that describes the watchdog function.

Care During Powering Up

• When powering up

When turning on the power supply, never fail to start from setting the RST pin to “L” level. And after the power

supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycle, then set to “H” level.

• Source oscillation input

At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing

waiting.

• Power on resetting

When powering up or when turning the power back on after the supply voltage drops below the operation

assurance range, be sure to reset the power.

• Power on sequence

Turn on the power in the order of VCC, AVCC and AVRH. The power should be disconnected in inverse order.

• Even when an A/D converter is not in use, connect AVCC to the VCC level and AVSS to the VSS level.

• Even when a D/A converter is not in use, connect DAVC to the VCC level and DAVS to the VSS level.

MB91F158

MB91F158 Datasheet(PDF) 13 Page - fujitsu semiconductor