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VIA Technologies, Inc.
Preliminary VT6508 Datasheet
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(3) bits 30..20: Packet Byte Count
(4) bits 34..31: Source Port ID
The number of packet buffers is determined by the configured SRAM size, listed as follows:
SRAM Size
128KB
256KB
512KB
1MB
maximum # of packet buffers
64 buffers
149 buffers
320 buffers
661 buffers
2.3 RMII INTERFACE
The VT6508 can directly connect to an 8 port RMII PHY device through the reduced
MII (RMII) interface to construct a small-sized system board. The signals of RMII interface
are described as follows:
Name
Type
Description
CRSDV
I
Carrier sense and Data
valid
RXD[0-1]
I
Receive data bit 0 to 1 ,
data rate with 50MHz
TXEN
O
Transmit Enable
TXD[0-1]
O
Transmit Data bit 0 to
1
2.3 MANAGEMENT INTERFACE AND AUTO NEGOTIATION
The VT6508 communicates with the external 10/100M PHY and access the PHY
register through MDC, MDIO
. The signals of management interface are described as follows:
Name
Type
Description
MDC
O
management interface
clock
MDIO
IO
management interface
data signal
Auto-polling state machine:
step1. Auto-polling idle
- if auto-polling_command=”on” then go to step2
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