2.4.2

I²C - inter-IC control interface

Subject to general operating conditions for Vdd and Top.

Table 6. I²C slave timing values

Symbol

Parameter

I²C standard mode(1)

I²C fast mode(1)

Unit

Min

Max

Min

Max

f(SCL)

SCL clock frequency

0

100

0

400

kHz

tw(SCLL)

SCL clock low time

4.7

1.3

µs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

ns

th(SDA)

SDA data hold time

0.01

3.45

0.01

0.9

µs

th(ST)

START condition hold time

4

0.6

µs

tsu(SR)

Repeated START condition setup time

4.7

0.6

tsu(SP)

STOP condition setup time

4

0.6

tw(SP:SR)

Bus free time between STOP and START condition

4.7

1.3

1. Data based on standard I²C protocol requirement, not tested in production.

Figure 4. I²C slave timing diagram

SDA

SCL

tsu(SP)

tw(SCLL)

tsu(SDA)

tsu(SR)

th(ST)

tw(SCLH)

th(SDA)

tw(SP:SR)

START

REPEATED

START

STOP

START

Note:

Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.

LIS2DU12

Communication interface characteristics

DB4522 - Rev 1

page 8/13