3.4

MCU sub system

The Cortex® M7 core masters the system resources (memories, registers, and external memory controllers)

through the AXI, AHB and APB interconnects present in the SOC.

3.4.1

Caches

The size of instruction and data cache used for ARM® sub-system in STA8135GA is 16 KB each.

3.4.2

TCM

ARM® Cortex® M7 has TCM Control Unit (TCU) with TCM interfaces and an AHB slave (AHBS) interface for

system access to TCMs. These TCM memories are integrated outside the ARM® sub-system. STA8135GA has

64 KB ITCM memory and 384 KB of DTCM memory.

In the DTCM memory 160 KB is dedicated for ARM® usage and remaining 224 KB DTCM is shared between the

ARM® sub-system and G5BB module.

ARM® provides access to TCM memories through an AHB slave interface. This AHBS interface is connected to

the AMBA infrastructure in STA8135GA so that DMA present on the bus can access the TCM memories MCU.

3.4.3

Nested Vector Interrupt Controller (NVIC)

This Nested Vectored Interrupt Controller (NVIC) allows the operative system interrupt handler to quickly dispatch

interrupt service routines in response to peripheral interrupts. It provides a software interface to the interrupt

system. ARM® Cortex® M7 has NVIC module for handling the interrupts. The NVIC supports 128 interrupts with

16 levels of priority, which can be changed dynamically. The software can control each request line to generate

software interrupts.

3.4.4

AXI bus

AXI Bus matrix handles major high bandwidth transactions for STA8135GA. It connects the SRAM, boot ROM and

external memory controllers, which provide access to the external Flash. ARM® acts as a master on this bus with

the highest priority.

3.5

APB peripherals

3.5.1

APB bridge 2 peripherals

AHB to APB Bridge 2 sits on AHB bus matrix 0 as a slave and is used to connect peripherals. These slaves will

be accessed by AHB masters connected to AHB bus matrix 0.

The peripherals connected to APB 2 are: UART2, MSP1, GPIO PORT 2, MTU1.

3.5.2

APB bridge 1 peripherals

AHB to APB bridge 1 sits on AHB bus matrix 0 as a slave and is used to connect peripherals. These slaves will be

accessed by AHB masters connected to AHB bus matrix0.

The peripherals connected to APB 1 are UART1, EFT0, EFT1, GPIO PORT 0 and 1, MTU0, OTP, SSP, Thermal

sensor, Watchdog timer.

3.5.3

APB bridge 0 peripherals

AHB to APB bridge 0 sits on AHB bus matrix 0 as a slave and is used to connect peripherals. These slaves will be

accessed by AHB masters connected to AHB bus matrix0.

The peripherals connected to APB 0 are the ones on the always on domain: PRCC always ON, RTC.

3.5.4

AHB slave devices

There are some AHB slave devices which are connected to AHB bus matrix 0.

STA8135GA

MCU sub system

DB4575 - Rev 1

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