APR34709

Document number: DS41354 Rev. 5 - 3

9 of 13

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APR34709

Synchronous Rectification Principle Description (continued)

Recommended Application Circuit Parameters

The CAREF is suggested to parallel with the AREF resistor to keep the volt-second product threshold stable. And the recommended value of CAREF

is 20nF.

The recommended value of C24 is 100nF. The value of VDD capacitor C23 is 4.7µF.

Green Mode at Light Load

When the system is running with light load, rectifier conduction loss no longer dominates the secondary-side power loss, in which condition it is

preferred the SR MOSFET keeps off to save the driver loss.

The APR34709 can sense the non-switching duration cycle by cycle, when the non-switching duration keeps longer than the internal light load

timing tLL, the IC will shut down the gate driver and keep it off for the next two cycles.

VDD

The VDD is the output of Pulse Linear Regulator and the internal linear regulator. It provides bias voltage for the controller. A capacitor (C23,

typical 4.7µF) should be connected between the VDD pin and GND pins.

A Pulse Linear Regulator is integrated in the controller to provided voltage to the VDD pin of the APR34709, so that the APR34709 can operate at

Constant Current (CC) Mode, in which the system output voltage may drop to as low as 2V. The bias voltage is disabled when system output

voltage is higher than 4.75V, in that case the system output provides voltage to VDD pin of the APR34709 through its internal LDO.