ES25P40 datasheet(19/35 Pages) EXCELSEMI

19 / 35 page

ES I

Rev. 0D May 11 , 2006

ES25P40

Excel Semiconductor inc.

ADVANCED INFORMATION

Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all

bits inside the chosen sector. Before it can be

accepted, a Write Enable (WREN) instruction must

previously have been executed. After the Write

Enable (WREN) instruction has been decoded, the

device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driv-

ing Chip Select (CS#) Low, followed by the instruc-

tion code, and three address bytes on Serial Data

Input (SI). Any address inside the Sector (see Table

1) is a valid address for the Sector Erase (SE)

instruction. Chip Select (CS#) must be driven Low for

the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

Chip Select (CS#) must be driven High after the

eighth bit of the last address byte has been latched

in, otherwise the Sector Erase (SE) instruction is

not executed. As soon as Chip Select (CS#) is

driven High, the self-timed Sector Erase cycle

(whose duration is tSE) is initiated. While the Sector

Erase cycle is in progress, the Status Register may

be read to check the value of the Write In Progress

(WIP) bit. The Write In Progress (WIP) bit is 1 dur-

ing the self-timed Sector Erase cycle, and is 0 when

it is completed. At some unspecified time before the

cycle is completed, the Write Enable Latch (WEL)

bit is reset.

A Sector Erase (SE) instruction applied to any

memory area that is protected by the Block Protect

(BP2, BP1, BP0) bits (see Table 1) is not executed.

Figure 14. Sector Erase (SE) Instruction Sequence

SCK

CS#

MSB

Instruction

24-Bit Address

23 22 21

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