WM8770SIFT datasheet(17/52 Pages) WOLFSON

17 / 52 page

Production Data

WM8770

PD Rev 4.1 June 2005

DEVICE DESCRIPTION

INTRODUCTION

WM8770 is a complete 8-channel DAC, 2-channel ADC audio codec, including digital interpolation

and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi-bit sigma delta

DACs with analogue volume controls on each channel and output smoothing filters.

The device is implemented as four separate stereo DACs and a stereo ADC with flexible input

multiplexor, in a single package and controlled by a single interface.

The four stereo channels may either be used to implement a 5.1 channel surround system, with

additional stereo channel for a stereo mix down channel, or for a complete 7.1 channel surround

system.

An analogue bypass path option is available, to allow stereo analogue signals from any of the 8

stereo inputs to be sent to the stereo outputs via the main volume controls. This allows a purely

analogue input to analogue output high quality signal path to be implemented if required. This would

allow, for example, the user to play back a 5.1 channel surround movie through 6 of the DACs, whilst

playing back a separate analogue or digital signal into a remote room installation.

Each stereo DAC has its own data input DIN1/2/3/4. DAC word clock DACLRC is shared between

them. The stereo ADC has it’s own data output DOUT, and word clock ADCLRC. BITCLK and MCLK

are shared between the ADCs and DACs. The Audio Interface may be configured to operate in either

master or slave mode. In Slave mode ADCLRC, DACLRC and BCLK are all inputs. In Master mode

ADCLRC, DACLRC and BCLK are all outputs.

The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC,

using external resistors to reduce the amplitude of larger signals to within the normal operating range

of the ADC. The ADC input PGA also allows input signals to be gained up to +19dB and attenuated

down to -12dB. This allows the user maximum flexibility in the use of the ADC.

A selectable stereo record output is also provided on RECL/R. It is intended that the RECL/R outputs

are only used to drive a high impedance buffer.

Each DAC has its own analogue and separate digital volume control. The analogue volume control is

adjustable in 1dB steps and the digital volume control in 0.5dB steps. The analogue and digital

volume controls may be operated independently. In addition a zero cross detect circuit is provided for

each DAC for both analogue and digital volume controls. When analogue volume zero-cross

detection is enabled the attenuation values are only updated when the input signal to the gain stage

is close to the analogue ground level. The digital volume control detects a transition through the zero

point before updating the volume. This minimises audible clicks and ‘zipper’ noise as the gain values

change.

Additionally, 6 of the DAC outputs incorporate an input selector and mixer allowing an external 6

channel, or 5.1 channel signal, to be either switched into the signal path in place of the DAC signal or

mixed with the DAC signal before the volume controls. This allows the device to be used as a 6

channel volume control for an externally provided 5.1 type analogue input. Use of external resistors

allows larger input levels to be accepted by the device, giving maximum user flexibility.

Control of internal functionality of the device is by 3-wire serial control interface. An SPI or CCB type

interface may used, selectable by the state of the CE pin on the rising edge of RESETB. The control

interface may be asynchronous to the audio data interface as control data will be re-synchronised to

the audio processing internally.

CE, CL, DI and RESETB are 5V tolerant with TTL input thresholds, allowing the WM8770 to used

with DVDD = 3.3V and be controlled by a controller with 5V output.

Operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided. In Slave

mode selection between clock rates is automatically controlled. In master mode the master clock to

sample rate ratio is set by control bits ADCRATE and DACRATE. ADC and DAC may run at different

rates within the constraint of a common master clock for the ADC and DACs. For example with

master clock at 24.576MHz, a DAC sample rate of 96kHz (256fs mode) and an ADC sample rate of

48kHz (512fs mode) can be accomadated. Master clock.Sample rates (fs) from less than 8ks/s up to

192ks/s are allowed, provided the appropriate system clock is input.

The audio data interface supports right, left and I

2S interface formats along with a highly flexible DSP

serial port interface.

WM8770SIFT Datasheet(PDF) 17 Page - Wolfson Microelectronics plc

WM8770SIFT Datasheet(HTML) 17 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL