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PI7C9X760ACLEX Datasheet(PDF) 33 Page - Diodes Incorporated

Part # PI7C9X760ACLEX
Description  I2C-bus/SPI to UART Bridge Controller w/ 64 bytes of TX/RX FIFOs
PDF  53 Pages
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Manufacturer  DIODES [Diodes Incorporated]
Direct Link  http://www.diodes.com
Logo DIODES - Diodes Incorporated

PI7C9X760ACLEX Datasheet(HTML) 33 Page - Diodes Incorporated

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www.diodes.com
April 2019
Diodes Incorporated
PI7C9X760
Document Number DS40305 Rev 6-2
A product Line of
Diodes Incorporated
PI7C9X760
Offset 0CH: GPIO Interrupt Enable Register (IOIntEna). Default=00
Bit
Type
Description
[7:0]
RW
This register enable the interrupt for GPIO pins. If GPIO[7:4] or GPIO[3:0] are programmed as mo-
dem pins, IOIntEna will have no effect on GPIO[7:4] or GPIO[3:0].
0 = disabled
1 = enabled
Offset 0EH: GPIO Control Register (IOControl). Default=00
Bit
Type
Description
[7:4]
RO
Reserved
3
RW
UART Software Reset.
Writing a logic 1 to this bit will reset the device.
This bit is automatically be reset after device is reset.
2
RW
GPIO[3:0] or Modem IO Select(CH B)
0 = GPIO[3:0] behave as GPIO pins
1 = GPIO[3:0] behave as RIB#,CDB#,DTRB#,DSRB#
1
RW
GPIO[7:4] or Modem IO Select(CH A)
0 = GPIO[7:4] behave as GPIO pins
1 = GPIO[7:4] behave as RIA#,CDA#,DTRA#,DSRA#
0
RW
This bit enable GPIO inputs latching
0 = GPIO input values are not latched. If the input goes back to its initial logic state before the input
register is read, then the interrupt is cleared.
1 = GPIO input values are latched. If the input goes back to its initial logic state before the input reg-
ister is read, then the interrupt is not cleared and the corresponding bit of IOState register keeps the
logic value that generated the interrupt.
Offset 0FH: Extra Features Control Register (EFCR). Accessable when SFR[2]=0, Default=00
Bit
Type
Description
7
RW
IrDA mode.
0 = IrDA version 1.0, 3/16 pulse ratio,data rate up to 115.2 Kbps
1 = IrDA version 1.1, 1/4 pulse ratio,data rate up to 1.152 Mbps
6
RO
Reserved
5
RW
Auto RS-485 Polarity Inversion
This bit changes the polarity of the Auto RS-485 Direction Control output(RTS#). it will only affect
the behavior of RTS# if EFCR[4]=1
0 = RTS# output is LOW when transmitting and HIGH when receiving
1 = RTS# output is HIGH when transmitting and LOW when receiving
4
RW
Auto RS-485 direction control
This bit enables the transmitter to control RTS# pin
0 = transmitter does not control RTS# pin
1 = transmitter controls RTS# pin
3
RO
Reserved
Configuration Registers cont..
Notes: GPIO registers(0AH-0EH) are channel independent. For example, setting software reset will reset all channels.



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