AX88195P datasheet(30/37 Pages) ASIX

30 / 37 page

ASIX ELECTRONICS CORPORATION

AX88195 Local CPU Bus Fast Ethernet MAC Controller

6.4.8 Asynchronous Memory I/F Access Timing

MEMORY WRITE

Tsu(A)

Th(A)

MEMA[15:1]

Tw(WR)

/MEMWR

Td(WtoR)

Tw(RDdis)

/MEMRD

Tsu(D)

Th(D)

Write Data

SD[15:0](Dout)

DATA Valid

Symbol

Description

Min

Typ.

Max

Units

Tsu(A)

ADDRESS SETUP TIME

Th(A)

ADDRESS HOLD TIME

0.3

Tw(WR)

WRITE PULSE WIDTH

Tw(RDdis)

READ DISABLE PULSE WIDTH

Td(WtoR)

WRITE TO READ DEALY

4.5

Tsu(D)

DATA SETUP TIME

Th(D)

DATA HOLD TIME

0.3

MEMORY READ

Tsu(A)

Th(A)

MEMA[15:1]

Referance

Tw(RD)

Internal

“/MEMRD”

( High Level )

/MEMWR

( Low Level )

/MEMRD

Tsu(RD)

Th(RD)

Read Data

MEMD[15:1]

Valid DATA

Symbol

Description

Min

Typ.

Max

Units

Tsu(A)

ADDRESS SETUP TIME

Th(A)

ADDRESS HOLD TIME

1.3

Tw(RD)

READ PULSE WIDTH

Tsu(D)

DATA SETUP TIME

Th(D)

DATA HOLD TIME

* NOTE : The pulse width can be seen as LCLK/XTALIN high time. See also 6.4.1 “Thigh” parameter.

NOTE : All most any brand asynchronous SRAM access time under 20 ns can fit into the specification.

AX88195P Datasheet(PDF) 30 Page - ASIX Electronics Corporation

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