9.4.9

PFC state machine event driven (SMED)

The PFC high frequency operations are managed by a programmable 8-state ”State Machine Event Driven” (2

coupled 4-state SMEDs).

The SMED controls the PFC MOSFET based on the PFC comparators output and internally controlled counters.

It generates also the comparators' enable signals. It works at 60 MHz.

9.5

PFC algorithm

The PFC operates based on a multi-mode scheme.

A constant on-time (COT) control is implemented; TON is calculated from the PFC feedback and the measured

Vin peak.

TON is calculated and updated at the line cycle valley.

Based on the working PFC's operating state variables the working mode is changed to optimize the overall

efficiency.

9.5.1

Ramp enhanced COT improved (patented)

The PFC control is based on the constant on-time scheme, with a proprietary improved algorithm: the calculated

TON is applied only after the PFC RECOT comparator is triggered to balance the recovery diode energy and the

EMI capacitor current.

The PFC RECOT comparator threshold is adjusted by the core with a 6-bit DAC and allows to apply the

programmed base and ramp (defined by user into NVM).

This feature allows improving the total harmonic distortion (THD) and the power factor (PF) of the application.

9.5.2

Operating modes

The PFC manager changes the operating modes by dynamically reconfiguring the SMEDs, obtaining optimal

performances in term of both efficiency and THD/PF.

•

Transition mode (TM mode)

•

Valley skipping

•

Discontinuous mode (DCM)

9.6

PFC protections

9.6.1

PFC OVP

In case the bulk voltage triggers the PFC OVP comparator, the system enters the fault state; the overvoltage

protection can be programmed as latched or not latched.

The device implements also software overvoltage protection (SW OVP) that allows turning off the PFC until the

next line valley in case the SW OVP threshold is reached. The SW OVP threshold is a NVM parameter.

9.6.2

PFC OCP2

If the PFC OC2 comparator is triggered, the PFC gate is truncated and remains off until the beginning of a

new line half cycle. In case the PFC OC2 comparator is triggered for more than a programmable number of

consecutive half line cycles the device enters the OCP2 fault and it is turned off.

The OCP2 fault can be programmed as latched or not latched.

9.6.3

Surge

When the surge comparator signal is high the PFC MOSFET is turned off and an interrupt is generated. The

device will turn on the PFC MOSFET at the new line half cycle if the surge comparator output is low.

9.6.4

PFC soft-start timeout

If the PFC soft-start is not finished after 1 s the system enters the PFC soft-start timeout fault state and it is turned

off. The fault is not latched.

STNRG011

PFC algorithm

DS12075 - Rev 4

page 17/31