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DRV8461SPWPR Datasheet(PDF) 77 Page - Texas Instruments |
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DRV8461SPWPR Datasheet(HTML) 77 Page - Texas Instruments |
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77 / 117 page  Figure 7-61. CTRL2 Control Register (continued) R/W-0b R/W-0b R/W-0b R/W-0b R/W-0110b Table 7-42. CTRL2 Control Register Field Descriptions Bit Field Type Default Description 7 DIR R/W 0b Direction input. When SPI_DIR = 1b, if DIR = 1b, motor moves in the forward direction; and when DIR = 0b, motor moves in the reverse direction. 6 STEP R/W 0b Step input. Logic 1b causes the indexer to advance one step, when SPI_STEP = 1b. This bit is self-clearing, automatically becomes 0b after writing 1b. 5 SPI_DIR R/W 0b 0b = Outputs follow input DIR pin for direction of stepping 1b = Outputs follow DIR bit in SPI register for direction of stepping 4 SPI_STEP R/W 0b 0b = Outputs follow input STEP pin for stepping 1b = Outputs follow STEP bit in SPI register for stepping 3-0 MICROSTEP_MODE [3:0] R/W 0110b • 0000b = Full step (2-phase excitation) with 100% current • 0001b = Full step (2-phase excitation) with 71% current • 0010b = Non-circular 1/2 step • 0011b = 1/2 step • 0100b = 1/4 step • 0101b = 1/8 step • 0110b = 1/16 step • 0111b = 1/32 step • 1000b = 1/64 step • 1001b = 1/128 step • 1010b = 1/256 step • 1011b to 1111b = Reserved 7.5.2.3 CTRL3 (address = 0x06) [Default = 38h] CTRL3 is shown in Figure 7-62 and described in Table 7-43. Read/Write Return to the Register Maps Table Figure 7-62. CTRL3 Control Register 7 6 5 4 3 2 1 0 CLR_FLT LOCK [2:0] TOCP OCP_MODE OTSD_MODE OTW_REP R/W-0b R/W-011b R/W-1b R/W-0b R/W-0b R/W-0b Table 7-43. CTRL3 Control Register Field Descriptions Bit Field Type Default Description 7 CLR_FLT R/W 0b Write 1b to this bit to clear all latched fault bits. This bit automatically resets to 0b after 1b is written. 6-4 LOCK [2:0] R/W 011b Write 110b to lock the settings by ignoring further register writes except to these bits and address 0x06h bit 7 (CLR_FLT). Writing any sequence other than 110b has no effect when unlocked. Write 011b to this register to unlock all registers. Writing any sequence other than 011b has no effect when locked. 3 TOCP R/W 1b 1b = Overcurrent protection deglitch time is 2.2 μs 0b = Overcurrent protection deglitch time is 1.2 μs www.ti.com DRV8461 SLOSE98 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: DRV8461 |
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