LTM8060 datasheet(13/28 Pages) AD

13 / 28 page

LTM8080

Rev. 0

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PGFBn (Pins G3, G4): Power Good Feedback. The PG pins

pull high if PGFB increases beyond 300mV on its rising

edge, with 7mV hysteresis on its falling edge. Connecting

an external resistor divider between VOUTn, PGFB, and

GND sets the programmable power good threshold with

the following transfer function: 0.3V • (1 + RPG1,3/RPG2,4).

As discussed in the Applications Information section,

PGFB activates fast start-up circuitry. Tie PGFB to VBUS

if power good and fast start-up functionalities are not

needed. A parasitic substrate diode exists between PGFB

and GND pins; do not drive PGFB more than 0.3V below

GND during normal operation or a fault condition.

VSNSn (Pins H2, H5): Output Sense. These pins are the

noninverting input to the error amplifier of the LDO. Kelvin

connects VSNSn directly to the output capacitor and the

load for optimal transient performance and load regula-

tion. Also, tie the GND connections of the output capacitor

and the SET pin capacitor directly together. A parasitic

substrate diode exists between VSNSn and GND pins; do

not drive VSNSn more than 0.3V below GND during regular

operation or a fault condition.

SETn (Pins H3, H4): These pins are the inverting input

of the error amplifier and the regulation set-point for

the LDOs. SET sources a precision 100µA current that

flows through an external resistor connected between

SET and GND. VSET = ISET • RSET determines the LDO’s

output voltage. The output voltage range is from zero to

8V. Adding a capacitor from SET to GND improves noise,

PSRR, and transient response at the expense of increased

start-up time. For optimum load regulation, Kelvin con-

nects the ground side of the SET pin resistor directly to

the load. A parasitic substrate diode exists between SET

and GND pins; do not drive SET more than 0.3V below

GND during regular operation or a fault condition.

PIN FUNCTIONS

LTM8060 Datasheet(PDF) 13 Page - Analog Devices