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AN213924 Datasheet(PDF) 21 Page - Infineon Technologies AG

Part # AN213924
Description  PSoC 6 MCU: CY8C61x5 Datasheet
PDF  74 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

AN213924 Datasheet(HTML) 21 Page - Infineon Technologies AG

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Document Number: 002-30703 Rev. *F
Page 20 of 73
PSoC 6 MCU: CY8C61x5 Datasheet
Figure 18 shows the high-level software overview. Cypress
provides middleware libraries for CapSense, ADC, and IDAC on
GitHub to enable quick integration. The Board Support Package
for any kit with CapSense capabilities automatically includes the
CapSense library in any application that uses the BSP.
User applications interact only with middleware to implement
functions of the CSD block. The middleware interacts with
underlying drivers to access hardware as necessary. The CSD
driver facilitates time-multiplexing of the CSD hardware if more
than one piece of CSD-related middleware is present in a project.
It prevents access conflicts in this case.
ModusToolbox Software provides a CapSense configurator to
enable fast library configuration. It also provides a tuner for
performance evaluation and real-time tuning of the system. The
tuner requires an EZI2C communication interface in the
application to enable real-time tuning capability. The tuner can
update configuration parameters directly in the device as well as
in the configurator.
CapSense and ADC middleware use the CSD interrupt to
implement non-blocking sensing and A-to-D conversion.
Therefore, interrupt service routines are a defined part of the
middleware, which must be initialized by the application.
Middleware and drivers can operate on either CPU. Cypress
recommends using the middleware only in one CPU. If both
CPUs must access the CSD driver, memory access should be
managed in the application.
Refer to AN85951: PSoC 4 and PSoC 6 MCU CapSense Design
Guide for more details on CSX sensing, CSD sensing, shield
electrode usage and its benefits, and capacitive system design
guidelines.
Refer to the API reference guides for CapSense, ADC, and IDAC
available on GitHub.
Figure 8. CapSense Software/Firmware Subsystem
Tuner
CSD Driver
GPIO / Clock
Drivers
CSD Block
GPIOs / Clock
SCB
SCB Driver
(EZI2C)
Configuration
Hardware and Drivers
Middleware
Software
Application Program



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