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ISL68226IRAZ Datasheet(PDF) 82 Page - Renesas Technology Corp

Part # ISL68226IRAZ
Description  Digital Triple Output, 8-Phase PWM Controller
PDF  96 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL68226IRAZ Datasheet(HTML) 82 Page - Renesas Technology Corp

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ISL68226
10. PMBus Command Detail
FN9329 Rev.1.00
Page 82 of 95
Oct.1.20
10.75 DMAADDR (C7h)
Definition: Specifies the target address of a DMA read or write to system memory. This command is used for
indirect access to any system memory.
Access: Global
Data Length in Bytes: 2
Data Format: Bit Field
Type: R/W
Default Value: 0000h
Units: N/A
10.76 PEAK_OC_LIMIT (CDh)
Definition: Sets the peak overcurrent limit thresholds for each phase within a rail. 0.1A per LSB.
Access: Paged
Data Length in Bytes: 2
Data Format: Direct
Type: R/W
Equation: Peak Phase OC Limit = (Direct value) / 10
Units: A
Default Value: 0258h (60A)
Range: Depends on configuration
Command
DMAADDR (C7h)
Format
Bit Field
Bit Position
15
14
13
12
11
10
987
6543
210
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
See Following Table
Default Value
0000
00000
0000
000
Bit
Field Name
Meaning
15:13
REGION
000 - RAM
12:0
DMAADDR
The 13-bit target address
Command
PEAK_OC_LIMIT (CDh)
Format
Direct
Bit Position
15
14
13
12
11
10
987
6543
210
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Two’s Complement Integer
Default Value
0000
00100
1011
000



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