Data Sheet

ADM4850 to ADM4857

Rev. F | Page 7 of 16

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. ADM4850, 8-Lead MSOP, Pin Configuration

Figure 4. ADM4850/ADM4851/ADM4852/ADM4853, 8-Lead SOIC,

Pin Configuration

Table 8. ADM4850/ADM4851/ADM4852/ADM4853, 8-Lead MSOP and 8-Lead SOIC, Pin Function Descriptions

Pin No.

Mnemonic

Description

1

RO

Receiver Output. When RO is enabled and (A − B) ≥ −30 mV, RO is high. When RO is enabled and (A − B) ≤ −200 mV,

RO is low.

2

RE

Receiver Output Enable. A low level on RE enables the receiver output (RO). A high level on RE places RO into a high

impedance state.

3

DE

Driver Output Enable. A high level on DE enables the driver differential outputs (A and B). A low level on DE places

the driver differential outputs into a high impedance state.

4

DI

Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, whereas a logic high on DI

forces A high and B low.

5

GND

Ground.

6

A

Noninverting Receiver Input A/Noninverting Driver Output A.

7

B

Inverting Receiver Input B/Inverting Driver Output B.

8

V

CC

5 V Power Supply.

RO

VCC

DI

GND

RE

B

DE

A

1

2

3

4

8

7

6

5

ADM4850

(Not to Scale)

TOP VIEW

VCC

1

A

8

GND

4

5

ADM4850/

ADM4851/

ADM4852/

ADM4853

TOP VIEW

(Not to Scale)

RO

2

B

7

DI

6

3

DE

RE