TPD7212FN

2020-07-03

7

© 2020

Toshiba Electronic Devices & Storage Corporation

7.3. Normal operation, Top and bottom short circuit input mode

Table 7.1 Truth table

EN

IN1

(IN2,3)

IN4

(IN5,6)

Charge

pump

circuit

Output voltage

DIAG1

output

DIAG2

output

Remarks

UU output

(VU,WU)

UB output

(VB,WB)

L

＊

＊

Operate

L

L

H

L

－

H

L

L

Operate

L

L

H

L

－

H

H

L

Operate

H

L

H

L

－

H

L

H

Operate

L

H

H

L

－

H

H

H

Operate

L(self-

return)

L(self-

return)

L(self-

return)

L

Top and bottom short

circuit input mode

＊：

Don’t care

When at least one of the paired high-side output control input and low-side output control input (IN1 and IN4,

IN2 and IN5, IN3 and IN6) is H, the top and bottom short circuit input mode is selected, and all outputs are L

DIAG1 is also L.

These self-return will be carried out if the corresponding input is out of the Top and bottom short circuit input

mode.

Figure 7.3 Normal operation, Top and bottom short circuit input mode