SST25VF020B datasheet(7/33 Pages) MICROCHIP

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DS20005054D-page 7

SST25VF020B

4.4.1

BUSY

The BUSY bit determines whether there is an internal

erase or program operation in progress. A ‘1’ for the

BUSY bit indicates the device is busy with an operation

in progress. A ‘0’ indicates the device is ready for the

next valid operation.

4.4.2

WRITE ENABLE LATCH (WEL)

The Write Enable Latch bit indicates the status of the

internal memory Write Enable Latch. If the Write

Enable Latch bit is set to ‘1’, it indicates the device is

write enabled. If the bit is set to ‘0’ (Reset), it indicates

the device is not write enabled and does not accept any

memory write (program/erase) commands. The Write

Enable Latch bit is automatically reset under the follow-

ing conditions:

• Power-Up

• Write Disable (WRDI) instruction completion

• Byte Program instruction completion

• Auto Address Increment (AAI) programming is

completed or reached its highest unprotected

memory address

• Sector Erase instruction completion

• Block Erase instruction completion

• Chip Erase instruction completion

• Write STATUS Register instructions

4.4.3

AUTO ADDRESS INCREMENT (AAI)

The Auto Address Increment Programming Status bit

provides status on whether the device is in AAI pro-

gramming mode or Byte Program mode. The default at

power-up is Byte Program mode.

4.4.4

BLOCK PROTECTION (BP1, BP0)

The Block Protection (BP1, BP0) bits define the size of

the memory area, as defined in Table 4-4, to be soft-

ware protected against any memory write (program or

erase) operation. The Write STATUS Register (WRSR)

instruction is used to program the BP1 and BP0 bits as

long as WP# is high or the Block Protect Lock (BPL) bit

is ‘0’. Chip Erase can only be executed if Block Protec-

tion bits are all ‘0’. After power-up, BP1 and BP0 are set

to ‘1’.

4.4.5

BLOCK PROTECTION LOCK-DOWN

(BPL)

WP# pin driven low (VIL) enables the Block Protection

Lock Down (BPL) bit. When BPL is set to ‘1’, it prevents

any further alteration of the BPL, BP1 and BP0 bits of

the STATUS register and BSP and TSP of STATUS

BPL bit has no effect and its value is “don’t care”. After

power-up, the BPL bit is reset to ‘0’.

4.4.6

TOP SECTOR

PROTECTION/BOTTOM SECTOR

PROTECTION

The Top Sector Protection (TSP) and Bottom Sector

Protection (BSP) bits independently indicate whether

the highest and lowest sector locations are write locked

or write accessible. When TSP or BSP is set to ‘1’, the

respective sector is write locked; when set to ‘0,’ the

respective sector is write accessible. If TSP or BSP is

set to ‘1’ and if the top or bottom sector is within the

boundary of the target address range of the program or

erase instruction, the initiated instruction (Byte pro-

gram, AAI Word program, Sector Erase, Block Erase

and Chip Erase) will not be executed. Upon power-up,

the TSP and BSP bits are automatically reset to ‘0’.

TABLE 4-4:

SOFTWARE STATUS REGISTER BLOCK PROTECTION(1)

Protection Level

STATUS Register Bit(2)

Protected Memory Address

BP1

BP0

2 Mbit

None

1 (1/4 Memory Array)

030000H-03FFFFH

1 (1/2 Memory Array)

020000H-03FFFFH

1 (Full Memory Array)

000000H-03FFFFH

Note 1: x = “don’t care” (RESERVED) default is ‘0’

2: Default at power-up for BP1 and BP0 is ‘11’ (all blocks protected)

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