XRT83SL216 datasheet(4/41 Pages) EXAR

4 / 41 page

XRT83SL216

PRELIMINARY

16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

REV. P1.0.3

TABLE OF CONTENTS

GENERAL DESCRIPTION .................................................................................................1

APPLICATIONS ...........................................................................................................................................1

FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL216 ........................................................................................................................... 1

FEATURES

......................................................................................................................................................2

PRODUCT ORDERING INFORMATION ..................................................................................................2

FIGURE 2. PIN OUT FOR THE XRT83SL216 (BOTTOM VIEW) ............................................................................................................. 3

TABLE OF CONTENTS ............................................................................................................ I

PIN DESCRIPTIONS ..........................................................................................................4

SERIAL MICROPROCESSOR INTERFACE ............................................................................................................4

RECEIVER SECTION........................................................................................................................................5

TRANSMITTER SECTION ..................................................................................................................................8

CONTROL FUNCTION ....................................................................................................................................11

JTAG SECTION............................................................................................................................................11

POWER AND GROUND ..................................................................................................................................12

1.0 RECEIVE PATH LINE INTERFACE .....................................................................................................15

FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH LINE TERMINATION (RTIP/RRING).................................................. 15

1.1 PEAK DETECTOR/DATA SLICER ................................................................................................................. 15

1.2 CLOCK AND DATA RECOVERY ................................................................................................................... 15

FIGURE 4. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK .............................................................................................. 15

FIGURE 5. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK ............................................................................................ 15

TABLE 1: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG .......................................................................................................... 16

1.3 RECEIVE SENSITIVITY .................................................................................................................................. 16

FIGURE 6. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY........................................................................................ 16

1.4 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ............................................................ 16

1.4.1 RLOS (RECEIVER LOSS OF SIGNAL)...................................................................................................................... 17

1.4.2 AIS (ALARM INDICATION SIGNAL) .......................................................................................................................... 17

1.4.3 LCV (LINE CODE VIOLATION DETECTION) ............................................................................................................ 17

1.5 RECEIVE JITTER ATTENUATOR .................................................................................................................. 17

1.6 HDB3 DECODER ............................................................................................................................................ 17

1.7 ARAOS (AUTOMATIC RECEIVE ALL ONES) ............................................................................................... 18

FIGURE 7. SIMPLIFIED BLOCK DIAGRAM OF THE ARAOS FUNCTION ................................................................................................ 18

1.8 RPOS/RNEG/RCLK ........................................................................................................................................ 18

FIGURE 8. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ..................................................................................... 18

FIGURE 9. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN........................................................................................ 18

2.0 TRANSMIT PATH LINE INTERFACE ..................................................................................................19

FIGURE 10. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH................................................................................................... 19

2.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 19

FIGURE 11. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ............................................................................................... 19

FIGURE 12. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ................................................................................................. 19

TABLE 2: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG ........................................................................................................... 20

2.2 HDB3 ENCODER ............................................................................................................................................ 20

TABLE 3: EXAMPLES OF HDB3 ENCODING...................................................................................................................................... 20

2.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 20

TABLE 4: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS .................................................................................... 20

2.4 TAOS (TRANSMIT ALL ONES) ...................................................................................................................... 21

FIGURE 13. TAOS (TRANSMIT ALL ONES) ...................................................................................................................................... 21

2.5 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ............................................................................................ 21

FIGURE 14. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................... 21

3.0 APPLICATIONS ...................................................................................................................................22

3.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 22

3.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 22

FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK ......................................................................................... 22

3.1.2 REMOTE LOOPBACK ................................................................................................................................................ 22

FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK.................................................................................................... 22

3.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 23

FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ..................................................................................................... 23

3.2 INTERFACING THE TRANSMIT SECTION OF THE XRT83L216 TO THE LINE ......................................... 23

FIGURE 18. INTERFACING THE XRT83L216 TO THE LINE FOR 75W APPLICATIONS (1 CHANNEL SHOWN) .......................................... 23

FIGURE 19. INTERFACING THE XRT83L216 TO THE LINE FOR 120 W APPLICATIONS (1CHANNEL SHOWN) ....................................... 24

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