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USB-DIO32HS

Specifications

Specifications

These specifications apply to both USB-DIO32HS standard and OEM versions

unless noted otherwise.

Digital Input/Output

Digital type: TTL

Number of I/O: 32 (2 ports of 16 bits)

Configuration: Bit-configurable as input (power on default) or output

Pull-up configuration: Each port has two 47 kΩ resistors configurable as a pull-up

or pull-down (default) with an internal jumper.

Jumper W3: configures port 0 bit 0 to bit 7

Jumper W4: configures port 0 bit 8 to bit 15

Jumper W5: configures port 1 bit 0 to bit 7

Jumper W6: configures port 1 bit 8 to bit 15

Digital I/O transfer rate

System-paced, asynchronous: 33 to 8000 port reads/writes or single bit reads/

writes per second typical, system dependent.

Synchronous: 0.022 Hz to 8 MHz, based on the internal clock speed of 96 MHz

Digital input pacing: Onboard clock, external input scan clock (ICLKI)

Digital input trigger source: External single channel digital trigger (TRIG) or

Pattern Detection

Digital output pacing: Onboard clock, external output scan clock (OCLKI)

Digital output trigger source: External single channel digital trigger (TRIG) or

Pattern Detection

Input high voltage: 2.0 V min, 5.0 V absolute max

Input low voltage: 0.8 V max, 0 V recommended min

Output high voltage: 4.4 V min (IOH = –50 µA), 2.96 V min (IOH = –24 mA)

Output low voltage: 0.1 V max (IOL = 50 µA), 0.77 V max (IOL = 10 mA)

Output current: 24 mA source, 10 mA sink max per pin, constrained to 384 mA

across all output pins (digital outputs, pacer clock outputs, and +VO)

Pattern Trigger

Trigger source: Port 0 or Port 1

Trigger types: Above pattern, Below pattern, Equal pattern, or Not equal pattern

Trigger stability: Digital port must be stable for 31.25 ns to be recognized as a pattern

Trigger bit width: Up to 16, adjustable through bitmask

Trigger latency: Up to 1 scan period

External Trigger

Trigger source: External digital; TRIG terminal

Trigger mode: Software-selectable for edge or level sensitive, rising or falling

edge, high or low level.

Retrigger mode: Trigger is rearmed after each trigger event

Trigger latency: 100 ns max

Trigger pulse width: 100 ns min

Input type: Schmitt trigger, 47 kΩ pull-down to ground with 33 Ω in series

Schmitt trigger hysteresis: 0.76 V typ, 0.4 V min, 1.2 V max

Input high voltage threshold: 1.74 V typ, 1.3 V min, 2.2 V max

Input high voltage limit: 5.5 V absolute max

Input low voltage threshold: 0.98 V typ, 0.6 V min, 1.5 V max

Input low voltage limit: –0.5 V absolute min, 0 V recommended min

Clock Input/Output

Terminal names: ICLKI, ICLKO, OCLKI, OCLKO

Terminal type

ICLKI: Input scan clock input, active on rising edge

ICLKO: Input scan clock output, power on default 0 V, active on rising edge

OCLKI: Output scan clock input, active on rising edge

OCLKO: Output scan clock output, power on default 0 V, active on rising edge

Input clock frequency: 8 MHz max

Input clock pulse width: 10.417 ns min

Input type: Schmitt trigger, 47 kΩ pull-down to ground with 33 Ω in series

Input Schmitt trigger hysteresis: 0.76 V typ, 0.4 V min, 1.2 V max

Input high voltage threshold: 1.74 V typ, 1.3 V min, 2.2 V max

Input high voltage limit: 5.5 V absolute max

Input low voltage threshold: 0.98 V typ, 0.6 V min, 1.5 V max

Input low voltage limit: –0.5 V absolute min, 0 V recommended min

Output clock frequency: 8 MHz max

Output clock pulse width: Minimum 62.5 ns at 8 MHz, varies with sample rate;

maintains 50% duty cycle using the internal clock. When using the external

clock, it follows the external clock input.

Output high voltage: 4.4 V min (IOH = –50 µA), 2.96 V min (IOH = –24 mA)

Output low voltage: 0.1 V max (IOL = 50 µA), 0.77 V max (IOL = 10 mA)

Output current: 24 mA source, 10 mA sink max per pin, constrained to 384 mA

across all output pins (digital outputs, pacer clock outputs, and +VO)

Handshaking: The TXACK output will have an 83.33 ns delay from the OCLKO

signal to ensure coherent data transfers between devices.

Input pacer clock input (ICLKI)

Trigger input (TRIG)

Input pacer clock output (ICLKO)

Output pacer clock input (OCLKI)

Output pacer clock output (OCLKO)

Data transfer output (TXACK)

DIO

16

16

+VO

DIO 16

DIO

protection

DIO

protection

16

Bitwise-programmable

digtial I/O with

byte-congurable

pull-ups

Bitwise-programmable

digtial I/O with

byte-congurable

pull-ups

D+/D–

Power

supplies

5 V

3.3 V

1.2 V

VBUS

(5 V)

3.3 V

Always on

Power

control

USB

port

Crystal

24 MHz

8-bit data bus

16-bit FIFO bus

Clock output

Microcontroller

with

USB 2.0

high-speed

interface

EEPROM

FPGA

USB-DIO32HS Block Diagram