SIP32433

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Vishay Siliconix

E22-0335. A, 15-Aug-2022

11

Document Number: 63175

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Fig. 32 - True Reverse Current Blocking

VIN = 12 V, VOUT Raised Up to 13.5 V

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OVERVIEW

The SIP32433A and SIP32433B are eFuses with comprehensive integrated control features that simplify the design and

increase the reliability of the circuitry connected to the switch.

The 32 m

 switches are designed to operate in the 2.8 V to 23 V range. An internally generated gate drive voltage ensures good

RON linearity over the input voltage operating range.

The devices start their operation by checking the VIN, VOUT, OVP, and EN / UVLO pins. When the voltages are in the ranges

without exceeding under- or over-voltage protection thresholds, the PGD open drain switch is off. A high level on the EN / UVLO

pin enables the internal MOSFET to start conducting and allows current to flow from IN to OUT. When EN / UVLO is held low,

the internal MOSFET is turned off.

After a successful turn-on sequence, the device now actively monitors its load current, input voltage, and protects the load from

harmful over-current, and over-voltage conditions. A built-in thermal sense circuit will detect junction over temperature and shut

down the switch for safety.

SWITCH ON / OFF, AND UNDER-VOLTAGE LOCK OFF PROTECTION - UVLO

EN / UVLO pin controls the on / off of the power switch. When EN / UVLO is at a logic high the switch is on. When EN / UVLO

is at a logic low, the switch is off.

The SIP32433A and SIP32433B implement under-voltage protection on the EN / UVLO to turn off the output. It is a user-defined

under-voltage protection setting to flexibly select the proper minimum applied voltage for the downstream load or the device’s

proper operation.

The diagram shows how a resistor divider from supply to GND can be used to set the UVLO set point for a given voltage supply

level.

Fig. 33

10 μs/div

V

OUT (5 V/div)

V

IN (5 V/div)

I

IN (0.5 A/div)

IN

GND

EN /

UVLO

R

EN1

R

EN2

Power

source

SIP32433