| Electronic Components Datasheet Search |
|
PCF8576DT Datasheet(PDF) 24 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PCF8576DT Datasheet(HTML) 24 Page - NXP Semiconductors |
|
24 / 41 page ![]() 2004 Dec 22 24 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D Table 5 Mode set option 1 Table 6 Mode set option 2 Table 7 Mode set option 3 Table 8 Load data pointer option 1 Table 9 Device select option 1 Table 10 Bank select option 1 (input) Table 11 Bank select option 2 (output) Table 12 Blink option 1 Table 13 Blink option 2 Note 1. Normal blinking is assumed when LCD multiplex drive modes 1 : 3 or 1 : 4 are selected. 7.9 Display controller The display controller executes the commands identified by the command decoder. It contains the device’s status registers and co-ordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. 7.10 Cascaded operation In large display configurations, up to 16 PCF8576Ds can be differentiated on the same I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). PCF8576Ds connected in cascade are synchronized to allow the backplane signals from only one device in the cascade to be shared. This arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other cascaded PCF8576Ds contribute additional segment outputs but their backplane outputs are left open-circuit (see Fig.19). LCD DRIVE MODE BITS DRIVE MODE BACKPLANE M1 M0 Static BP0 0 1 1 : 2 BP0, BP1 1 0 1 : 3 BP0, BP1, BP2 1 1 1 : 4 BP0, BP1, BP2, BP3 0 0 LCD BIAS BIT B 1 ⁄3 bias 0 1 ⁄2 bias 1 DISPLAY STATUS BIT E Disabled (blank) 0 Enabled 1 DESCRIPTION BITS 6 bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0 DESCRIPTION BITS 3 bit binary value of 0 to 7 A2 A1 A0 MODE BIT I STATIC 1 : 2 RAM bit 0 RAM bits 0 and 1 0 RAM bit 2 RAM bits 2 and 3 1 MODE BIT O STATIC 1 : 2 RAM bit 0 RAM bits 0 and 1 0 RAM bit 2 RAM bits 2 and 3 1 BLINK FREQUENCY BITS BF1 BF0 Off 0 0 2Hz 0 1 1Hz 1 0 0.5 Hz 1 1 BLINK MODE BIT A Normal blinking 0 Alternate RAM bank blinking 1 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |