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P4C168, P4C169, P4C170
36
Notes:
7. ADDRESS must be valid prior to, or coincident with
CE/CS transition
low. For Fast
CS, t
AA must still be met.
8. Transition is measured
±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 2 (
CE
CE
CE
CE
CE/CS
CS
CS
CS
CS CONTROLLED)(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (
OE
OE
OE
OE
OE CONTROLLED)(5)
ADDRESS
tRC
(9)
1521 05
OE
tAA
t
CS
OE
t
OH
t
AC
t
OHZ
t
(8)
(8)
DATA OUT
tHZ
tLZ
(8)
(8)
OLZ
READ CYCLE WAVEFORM NO. 2 (
CS Controlled)
t
CE/CS
DATA OUT
AC
tRC
t LZ
(5,7)
DATA VALID
tOLZ
HIGH IMPEDANCE
(7)
(7)
tHZ
(7)
tOHZ
OE
(7)
I CC
I SB
tPU
tPD
SUPPLY
CC
CURRENT
V
WE
(P4C170)
(P4C168 ONLY)
tRCS
tRCH
t OE
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