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EM4102

Copyright © 2005, EM Microelectronic-Marin SA

5

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Memory Array for PSK encoding ICs

The PSK coded IC's are programmed with odd parity for

P0 and P1 and always with a logic zero.

The parity bits from P2 to P9 are even.

The column parity PC0 to PC3 are calculated including

the version bits and are even parity bits.

Code Description

Manchester

There is always a transition from ON to OFF or from OFF

to ON in the middle of bit period. At the transition from

logic bit “1” to logic bit “0” or logic bit “0” to logic bit “1” the

phase change.

Value high of data stream presented

below modulator switch OFF, low represents switch ON

(see Fig. 6).

Biphase Code

At the beginning of each bit, a transition will occur. A logic

bit “1” will keep its state for the whole bit duration and a

logic bit “0” will show a transition in the middle of the bit

duration (see Fig. 7).

PSK Code

Modulation switch goes ON and OFF alternately every

period of carrier frequency. When a phase shift occurs, a

logical "0" is read from the memory. If no shift phase

occurs after a data rate cycle, a logical "1" is read (see

Fig. 8).

Manchester Code

X

1

1

1

1

1

1

1

1

1

0

1

0

1

0

0

0

1

1

0

Modulation control "low" means high current

Binary data

Memory output

Modulator control

Fig. 6

Biphase Code

0

1

10

1001

Binary data

Memory output

Modulator control

Modulation control "low" means high current

Fig. 7

PSK Code

"0" ON SERIAL OUT

"1" ON SERIAL OUT

Modulator control

COIL1

Serial Data Out

Modulation control "low" means high current

Fig. 8