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LIS2DUX12 Datasheet(PDF) 59 Page - STMicroelectronics

Part # LIS2DUX12
Description  Ultralow-power accelerometer with AI & anti-aliasing
PDF  102 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LIS2DUX12 Datasheet(HTML) 59 Page - STMicroelectronics

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8.48
TAP_CFG2 (71h)
R/W
Table 118. TAP_CFG2 register
POST_STILL
_T5
POST_STILL
_T4
WAIT_T5
WAIT_T4
WAIT_T3
WAIT_T2
WAIT_T1
WAIT_T0
Table 119. TAP_CFG2 register description
POST_STILL_T[5:4]
Number of samples during stationary condition after shock and wait phases. These bits are used
together with POST_STILL_T[3:0] in register TAP_CFG1 (70h). 1 LSB = 4 samples (maximum 252
samples).
WAIT_T[5:0]
These bits program the number of samples to wait for the shock to finish.
1 LSB = 2 samples (maximum 126 samples).
8.49
TAP_CFG3 (72h)
R/W
Table 120. TAP_CFG3 register
POST_STILL
_THS3
POST_STILL
_THS2
POST_STILL
_THS1
POST_STILL
_THS0
LATENCY_T3 LATENCY_T2 LATENCY_T1 LATENCY_T0
Table 121. TAP_CFG3 register description
POST_STILL_THS[3:0](1)
Threshold for stationary condition after shock and wait phases. 1 LSB = 62.5 mg (maximum
937.5 mg)
LATENCY_T[3:0]
Maximum number of samples between consecutive taps event to detect double or triple tap. The
default value of these bits is 0000b which corresponds to 16 samples. If the LATENCY_T[3:0] bits
are set to a different value, 1LSB corresponds to 32 samples (maximum 480 samples).
1. The POST_STILL_THS[3:0] field must be set to a value greater than 0.
8.50
TAP_CFG4 (73h)
R/W
Table 122. TAP_CFG4 register
WAIT_END_
LATENCY
0
PEAK_THS5
PEAK_THS4
PEAK_THS3
PEAK_THS2
PEAK_THS1
PEAK_THS0
Table 123. TAP_CFG4 register description
WAIT_END_LATENCY
This bit enables the feature to wait for the end of the latency window to exclusively determine if the
event is a single, double or triple tap.
(0: tap event flag is raised immediately for every detected tap;
1: in case of consecutive taps, only the flag for the highest level of tap is raised. The tap event flag
is raised immediately if the highest level of tap enabled in TAP_CFG5 (74h) (single, double or triple)
is reached, otherwise it is raised at the end of the latency window if no additional taps are detected
within the window.)
PEAK_THS[5:0]
Threshold for peak detection. 1 LSB = 62.5 mg (maximum 3937.5 mg)
LIS2DUX12
TAP_CFG2 (71h)
DS14071 - Rev 2
page 59/102



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