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7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing

Figure 7-4 describes the device power-down sequencing.

J7VCL_ELCH_02

VDD_CPU

MCU_PORz

(J)

OSC1_XI, OSC1_XO

(optional)

WKUP_LFOSC0_XI, WKUP_LFOSC0_XO

(optional)

WKUP_OSC0_XI, WKUP_OSC0_XO

VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C

MCU_BOOTMODE[9:0], BOOTMODE[7:0]

Δ1

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,

VDDSHV0, VDDSHV2, VDDSHV5 ) , VDDA_3P3_USB

(D) (B)

(E)

(VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU,

VDDSHV0, VDDSHV2, VDDSHV5 ) ,VDDS_MMC0

(D) (C)

VDD_MCU , VDD_MCU_WAKE1, VDD_CORE,

(I)

VDD_WAKE0, VDDA_0P8_SERDES,

VDDA_0P8_SERDES_C, VDDA_0P8_USB,

VDDAR_CORE, VDDAR_CPU, VDDAR_MCU

(I)

VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0

(H)

(VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU,

VDDA_POR_WKUP, VDDA_WKUP, VDDA_OSC1,

VDDA_PLLGRP8, VDDA_PLLGRP6,VDDA_PLLGRP4,

VDDA_PLLGRP0, VDDA_TEMP0, VDDA_TEMP1)

(F)

(VDDA_1P8_SERDES, VDDA_1P8_USB)

(G)

PORz

(J)

Valid Configuration

Time stamp markers:

•

T0 – MCU_PORz & PORz assert low to put all processor resources in safe state. (0 ms)

•

T1 – Main DDR, SRAM Core, and SRAM CPU power supplies start ramp-down. (0.5 ms)

•

T2 – Low voltage core supplies start supply ramp-down. (2.5 ms)

•

T3 - 1.8-V voltages start supply ramp-down. (3.0 ms)

•

T4 – 3.3V voltages start supply ramp-down. (3.5 ms)

Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3 V to support 3.3-V digital interfaces.

Any MCU or Main dual voltage IO domains (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8 V to support 1.8-V digital interfaces.

VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3 V/1.8 V) power rail is required for compliant, high-speed

SD card operations. If SD card is not needed or standard data rates with fixed 3.3-V operation is acceptable, then domain can be

grouped with digital IO 3.3-V power rail. If a SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO

1.8-V power rail.

VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended

to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated,

then domain can be grouped with 3.3-V digital IO power rail either directly or through a supply filter.

VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply

for optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency

switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>

domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required .

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AM69A

SPRSP92 – FEBRUARY 2023

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