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Table 7-39. GPMC Timing Conditions

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

Input Conditions

SRI

Input slew rate

1.65

V/ns

Output Conditions

Output load capacitance

PCB Connectivity Requirements

td(Trace Delay)

Propagation delay of each trace 133 MHz

Synchronous Mode

140

360

All other modes

140

720

td(Trace Mismatch Delay)

Propagation mismatch across all traces

200

7.10.5.10.1 GPMC and NOR Flash — Synchronous Mode

Section 7.10.5.10.1.1 and Section 7.10.5.10.1.2 assume testing over the recommended operating conditions

and electrical characteristic conditions below (see Figure 7-51 through Figure 7-55).

7.10.5.10.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode

NO.

PARAMETER

DESCRIPTION(2)

MODE(3)

MIN

MAX

MIN

MAX

UNIT

100 MHz(4)

133 MHz(4)

F12 tsu(dV-clkH)

Setup time, input data

GPMC_AD[15:0] valid before

output clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.81

1.11

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.06

F13 th(clkH-dV)

Hold time, input data

GPMC_AD[15:0] valid after

output clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.78

2.28

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.78

F21 tsu(waitV-clkH)

Setup time, input wait

GPMC_WAIT[j] valid before

output clock GPMC_CLK high(1)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.81

1.11

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.06

F22 th(clkH-waitV)

Hold time, input wait

GPMC_WAIT[j] valid after output

clock GPMC_CLK high(1)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.78

2.28

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.78

(1)

In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3.

(2)

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-

Purpose Memory Controller (GPMC) section in the device TRM.

(3)

For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

–

GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100 MHz

•

For TIMEPARAGRANULARITY_X1:

www.ti.com

AM69A

SPRSP92 – FEBRUARY 2023

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