ADC34RF52 datasheet(48/105 Pages) TI

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7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band

Table 7-30 lists the available JESD204B formats and corresponding valid sampling rate ranges for the

ADC34RF52. The sampling rates are limited by the minimum and maximum SERDES line rate as well as

ADC sampling clock frequencies. The JESD204B frame assembly for the different lanes is shown in Table 7-31.

Table 7-30. JESD Mode Options: Real Decimation

DECIMATION

SETTING D

(complex)

MIN FS

(Gsps)

MAX FS

(Gsps)

RATIO

[fSERDES/(FS/D)]

0.5

1.5

/16

0.8

0.5

1.5

/16

/32

0.8

0.5

1.3

1.5

/16

/32

/64

0.8

0.5

1.3

/16

1.5

/32

/64

/128

0.8

Table 7-31. JESD Sample Frame Assembly: Real Decimation - Single Band

OUTPUT

LANE

LMFS = 8422

LMFS = 4421

LMFS = 2441

LMFS = 1481

DOUT0

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

DOUT1

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

DOUT2

[15:8]

[7:0]

[15:8]

[7:0]

DOUT3

[15:8]

[7:0]

[15:8]

[7:0]

DOUT4

[15:8]

[7:0]

DOUT5

[15:8]

[7:0]

DOUT6

[15:8]

[7:0]

DOUT7

[15:8]

[7:0]

ADC34RF52

SBASAI7 – MARCH 2023

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