HC705JJ7GRSSLASHD datasheet(218/230 Pages) NXP

218 / 230 page

Electrical Speciﬁcations

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Electrical Specifications

15.17 Reset Characteristics

Figure 15-2. Stop Recovery Timing Diagram

Characteristic

Symbol

Min

Typ

Max

Unit

Low-Voltage Reset

Rising Recovery Voltage

Falling Reset Voltage

LVR Hysteresis

VLVRR

VLVRF

VLVRH

2.4

2.3

100

3.4

3.3

—

4.4

4.3

—

POR Recovery Voltage (see Note 2)

VPOR

—

100

POR VDD Slew Rate (see Note 2)

Rising (see Note 2)

Falling (see Note 2)

SVDDR

SVDDF

—

0.1

0.05

µs

RESET Pulse Width (when Bus Clock Active)

tRL

1.5

—

tCYC

RESET Pulldown Pulse Width

(from Internal Reset)

tRPD

3—4

tCYC

NOTE:

+2.7

≤ V

DD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted

By design, not tested

PCH

NEW

1FFE

OSC1

RESET

Internal

Clock3

Internal

Address

Bus3

4064 or 16 t

cyc

NOTES:

1. Represents the internal gating of the OSC1 pin

2. Normal delay of 4064 tCYC or short delay option of 16 tCYC

3. Internal timing signal and data information not available externally

Internal

Data

Bus3

1FFF

NEW PCH

NEW PCL

PCL

NEW

code

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D Datasheet(PDF) 218 Page - NXP Semiconductors

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