VSC8541-01 datasheet(20/100 Pages) MICROSEMI

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Functional Descriptions

VMDS-10496 VSC8541-01 Datasheet Revision 4.2

•

0.13, 0.6—Forced speed selection

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0.12—Enable autonegotiation

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0.8—Duplex

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0.9:8—1000BASE-T capability

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23.12:11—MAC interface selection

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19E1.3:2—Force MDI crossover

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20E2.6:4—RX_CLK delay

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20E2.2:0—TX_CLK delay

Additionally, the following registers are set to 1 by default in unmanaged mode.

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28.6—ActiPHY enable

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20E1.4—Link speed autodownshift enable

3.3.3.1

Signals A and B

Signals A and B are used to set the RGMII RX_CLK and TX_CLK (GTX_CLK) delay settings (as defined

in register 20E2), as per the following table.

3.3.3.2

Signals C and D

Signals C and D are used to select the link advertisement settings, as defined in the following table.

3.3.3.3

Signal E

Signal E is used to select between RMII and RGMII MAC interface modes. When the state of Signal E is

latched to logic 0 on the rising edge of reset, the device operates in RGMII mode. When the state of

Signal E is latched to logic 1 on the rising edge of reset, the device operates in RMII mode.

Note: RMII only supports 10/100 Mbps speeds. When RMII mode is selected, the link advertisement selection

must also be changed to either 01, 10, or 11 settings, as defined in Table 9, page 10.

Note: Correct configuration of the device is an end user responsibility, and no attempt is made in the device to

disallow incorrect configurations.

Additionally, in unmanaged mode, the following settings are changed from their default values:

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Enable link speed downshift (register 20E1.4 set to 1)

•

Enable ActiPHY (register 28.6 set to 1)

3.3.3.4

PHY Address Bit 0/1 Selection in Unmanaged Mode

The RXD4 and RXD5 pins can be pulled LOW or HIGH externally to set the bit 0 and bit 1 of the device

PHY address. The upper 3 bits of the PHY address are always set to 0, and the lower 2 bits can be set to

Table 8 •

Signals A and B

Signals A, B

RX_CLK and TX_CLK Delay Setting

0, 0

000 - 0.2 ns

0, 1

010 - 1.1 ns

1, 0

100 - 2.0 ns

1, 1

110 - 2.6 ns

Table 9 •

Signals C and D

Signals C, D

Link Advertisement

0, 0

Default mode of operation, 10/100/1000 FDX/HDX, autoneg ON

0, 1

10/100 FDX/HDX, autoneg ON (disable 1000BT advertisements)

1, 0

100BTX, HDX forced mode, autoneg OFF

1, 1

10BT, HDX forced mode, autoneg OFF

VSC8541-01 Datasheet(PDF) 20 Page - Microsemi Corporation

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