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STM32H7B0AB Datasheet(PDF) 105 Page - STMicroelectronics

Part # STM32H7B0AB
Description  32-bit Arm® Cortex®-M7 280 MHz MCUs, 128-Kbyte Flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  205 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H7B0AB Datasheet(HTML) 105 Page - STMicroelectronics

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Speed Symbol
Parameter
conditions
Min(1) Max(1) Unit
01
Fmax(2)
Maximum frequency
C=50 pF, 1.62 V≤VDD≤2.7 V
-
50
MHz
C=30 pF, 1.62 V≤VDD≤2.7 V
-
58
C=10 pF, 1.62 V≤VDD≤2.7 V
-
66
tr/tf(3)
Output high to low level fall time and output low to
high level rise time
C=50 pF, 1.62 V≤VDD≤2.7 V
-
6.6
ns
C=30 pF, 1.62 V≤VDD≤2.7 V
-
4.8
C=10 pF, 1.62 V≤VDD≤2.7 V
-
3
10
Fmax(2)
Maximum frequency
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
-
55
MHz
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
-
80
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
-
133
tr/tf(3)
Output high to low level fall time and output low to
high level rise time
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
-
5.8
ns
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
-
4
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
-
2.4
11
Fmax(2)
Maximum frequency
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
-
60
MHz
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
-
90
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
-
175
tr/tf(3)
Output high to low level fall time and output low to
high level rise time
C=50 pF, 1.62 V≤VDD≤2.7 V(4)
-
5.3
ns
C=30 pF, 1.62 V≤VDD≤2.7 V(4)
-
3.6
C=10 pF, 1.62 V≤VDD≤2.7 V(4)
-
1.9
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3 T, skew ≤ 1/20 T, 45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
Analog switch between ports Pxy_C and Pxy
PA0_C, PA1_C, PC2_C and PC3_C can be connected internally to PA0, PA1, PC2 and PC3, respectively (refer to
SYSCFG_PMCR register in RM0468 reference manual). The switch is controlled by VDDSWITCH voltage level.
It is defined through BOOSTVDDSEL bit of SYSCFG_PMCR. If the switch is closed the switch characteristics are
given in the table below.
Table 68. Pxy_C and Pxy analog switch characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Switch impedance
Switch control boosted
-
-
315
Ω
Switch control not boosted
VDDSWITCH > 2.7 V
-
-
315
VDDSWITCH > 2.4 V
-
-
335
VDDSWITCH > 2.0 V
-
-
390
VDDSWITCH > 1.8 V
-
-
445
VDDSWITCH > 1.62 V
-
-
550
6.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see
Table 63. I/O static characteristics).
Unless otherwise specified, the parameters given in Table 69. NRST pin characteristics are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized in Table 20. General
operating conditions.
STM32H7B0xB
Operating conditions
DS13196 - Rev 7
page 105/205



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