VN9D5D20F datasheet(28/96 Pages) STMICROELECTRONICS

28 / 96 page

To turn on channels, information must enter into the following registers:

•

Select the PWM frequency by using the two bits PWMFCYx

•

Select the PHASE information by using the 5 bits CHPHAx

•

Select the switching slope by using the two bits SLOPECRx

•

Select the channels configuration Bulb/LED by using the bit CCR

•

Select the DUTYCYCLE information by using the 10 bits of the OUTCTRCRx registers

•

Select the channel through the dedicated register “SOCR” in the channel control register

•

Select the PWM triggering mode by using the single bit PWM_TRIG of the CTRL register

The PWMSYNC bit resets the internal 12 bits clock counter. This allows to have a known time base and to

synchronize different devices among each other.

The signal on the PWMCLK is divided internally by a factor from 4096 to 512 depending on the PWMFCY register

to generate the base frequency for the output.

•

PWM signal is generated by properly selecting 10 of 12 bits on the clock counter. PWM engine has a virtual

10-bit granularity except when PWM divider is set to 512, in this case only a 9-bit granularity is possible

(LSB of 10bit generated PWM is fixed to zero). Duty cycle step can be modified with the granularity related

to the 9-bit register.

The duty cycle of the output signal is configured for each OUTPUTX with the OUTCTRCR register using 10 bits

(MSB first).

•

Programming an output duty cycle at 000h results in a 0% duty cycle, it means the channel always OFF

depending on the SOCR/DIx bit setting

•

Programming an output duty cycle at 3FFh results in a 100% duty cycle (4095/4096), it means the channel

always ON when the SOCR/DIx bit is set.

–

In normal mode the outputs are driven according to the SPI register setting and INx pins (DIx in OR

with SPI) if the related DIENCR bit is set.

Set PWMSYNC bit in control register “CTRL” (to synchronize the internal PWM counter to the selected channels).

The internal PWM counter is 12 bits depth, it is active whatever the state of the channels, if VDD > VDD_POR_ON.

The set of PWMSYNC bit allows to reset the PWM counter.

The phase shift of the output signal is configured for each OUTPUTx by internally concatenating the CHPHAx 5

bits with '00000' in order to get 10 bits (5 bits + 0000). Granularity of the phase shift is 5 bits. CHPHA = 00000b

means a phase shift of 0 (internal 10bit phase shift is 0x000=0000000000b), while CHPHA = 11111b results in

a maximum phase shift of 31/32 =(internal 10bit phase shift is 0x3E0=0000000000b). The phase shift is relative

to the base frequency of the selected channel. Thus, the exact point in time when the channel switches on also

depends on the operating mode of the selected channel.

Table 31. Phase shift configuration

Phase shift

(%)

5 bits register

(H)

10 bits register

(H)

Phase shift (ms)

PWM = 400 kHz

divider = 2048

Phase shift (ms)

PWM = 400 kHz

divider = 1024

Phase shift (ms)

PWM = 400 kHz

divider = 512

9.4

0.481

0.24

0.12

28.1

120

1.439

0.719

0.360

46.9

1E0

2.40

1.2

0.6

2E0

3.84

1.92

0.96

380

4.608

2.304

1.152

A change of phase/duty will be taken in account after the next zero-crossing of the PWM counter.

Note:

If the frequency on PWMCLK is too low (f < PWM_Clk), the device falls back to an internally generated PWM

frequency of approximately 400 kHz. In this case, the PWMCLOCKLOW bit in the OUTSRx is set.

Example 1:

Below, an example with a 65% duty cycle, PWM divider = 2048 and a 25% phase is given with a PWM sampling

mode on the rising edge (PWM_TRIG = 0):

VN9D5D20F

Outputs control

DS12936 - Rev 6

page 28/96

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