ACTS373MS

FN4000 Rev 0.00

Page 7 of 10

April 1995

Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger and AC Load Circuit

Three-State High Timing Diagram and Load Circuit

Three-State Low Timing Diagram and Load Circuit

INPUT

VIL

VIL

VS

VIH

INPUT CP

VIH

TH = HOLD TIME

TSU = SETUP TIME

TW = PULSE WIDTH

TW

TSU

TH

TW

VS

DUT

TEST

CL

RL

POINT

50pF

500



PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS

PARAMETER

ACTS

UNITS

VCC

4.50

V

VIH

3.00

V

VS

1.30

V

VIL

0

V

GND

0

V

TPHZ

INPUT

VS

TPZH

VT

VIH

VSS

VOH

VOZ

OUTPUT

VW

DUT

TEST

CL

RL

POINT

50pF

500



PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS

PARAMETER

ACTS

UNITS

VCC

4.50

V

VIH

3.00

V

VS

1.30

V

VT

1.30

V

VW

3.60

V

GND

0

V

TPLZ

INPUT

VS

TPZL

VT

VIH

VSS

VOZ

VOL

OUTPUT

VW

CL

RL

DUT

TEST

POINT

VCC

500



50pF

PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS

PARAMETER

ACTS

UNITS

VCC

4.50

V

VIH

3.00

V

VS

1.30

V

VT

1.30

V

VW

0.90

V

GND

0

V