AT25SL321 datasheet(17/82 Pages) RENESAS

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DS-AT25SL321-112 Rev. J

Page 17

Nov 1, 2022

AT25SL321 Datasheet

Commands

The SPI command set of the AT25SL321 consists of thirty eight basic commands and the QPI command set

of the AT25SL321 consists of thirty- one basic commands that are fully controlled through the SPI bus (see

Command Set Table 5 and Table 6). Commands are initiated with the falling edge of Chip Select (CS). The

first byte of data clocked into the input pins (SI or IO [3:0]) provides the command code. Data on the SI input

is sampled on the rising edge of clock with most significant bit (MSB) first.

Commands are completed with the rising edge of edge CS. Clock relative timing diagrams for each command

are included in Figure 4 through Figure 64. All read commands can be completed after any clocked bit. However,

all commands that Write, Program or Erase must complete on a byte (CS driven high after a full 8-bit have been

clocked) otherwise the command needs to be terminated. This feature further protects the device from inadvertent

writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being

written, all commands except for Read Register are ignored until the program or erase cycle has completed.

Table 5. Manufacturer and Device Identification

ID code

Command

Manufacturer ID

Renesas Electronics

1Fh

90h, 92h, 94h, 9Fh

Device ID

AT25SL321

15h

90h, 92h, 94h, ABh

Memory Type ID

SPI / QPI

42h

9Fh

Capacity Type ID

32M

16h

9Fh

AT25SL321 Datasheet(PDF) 17 Page - Renesas Technology Corp