Symbol

Parameters

Test conditions

Min.

Typ.

Max.

Unit

tDACC

DOUT access time after SCLK

falling edge

20

35

ns

tDHLD

DOUT hold time after SCLK

falling edge

7

13

ns

tDS

DIN set-up time prior to SCLK

rising edge

10

ns

tDH

DIN hold time after SCLK rising

edge

10

ns

tDIS

CS rising edge to DOUT high-

impedance

DOUT falling

12

20

ns

DOUT rising

12

20

tCH

Min. SCLK high time

0.4 x

tSCLK

ns

tCL

Min. SCLK low time

0.4 x

tSCLK

ns

1. Datasheet minimum and maximum specification limits are specified by design, characterization or statistical analysis.

2. Timings are given with thresholds set to 50% of clock signals and 10% or 90% of data signals.

ADC1283

Electrical characteristics

DS13932 - Rev 1

page 6/24