CD40174BMS

Rev X.00

Page 8 of 8

Jan 13, 2017

CD40174BMS

FIGURE 8. TYPICAL PROPAGATION DELAY TIME (CLOCK TO OUTPUT) AS A FUNCTION OF LOAD CAPACITANCE

Typical Performance Curves (Continued)

AMBIENT TEMPERATURE (TA) = +25oC

SUPPLY VOLTAGE (VDD) = 5V

10V

15V

LOAD CAPACITANCE (CL) (pF)

0

1020304050

60708090

100

0

25

50

75

100

125

150

175

200

Waveform

FIGURE 9. DEFINITION OF SETUP, HOLD, PROPAGATION

DELAY, AND REMOVAL TIMES

CLOCK

INPUT

DATA

INPUT

OUTPUT

VDD

CLEAR

0

90%

50%

10%

VDD

50%

50%

0

0

0

tr CL

tf CL

tH(HL)*

tH(LH)*

tSU(HL)*

tSU(LH)*

tTLH

tTHL

tPHL

tPLH

tREM

90%

50%

10%

VDD

VDD

*(LH) OR (HL) OPTIONAL

Pad Layout

DIMENSIONS AND PAD LAYOUT FOR CD40174BMSH

The photographs and dimensions of each CMOS chip represent a chip when it

is part of the wafer. When the wafer is separated into individual chips, the angle

of cleavage may vary with respect to the chip face for different chips. The actual

dimensions of the isolated chip, therefore, may differ slightly from the nominal

dimensions shown. The user should consider a tolerance of -3 mils to +16 mils

applicable to the nominal dimensions shown.

Dimension in parenthesis are in millimeters and are derived from the basic inch

dimensions as indicated. Grid graduations are in mils (10-3 inch).

METALLIZATION: Thickness: 11k

Å 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6k

Å, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches